Motorola MVME2400 Series Manuel de service télécharger pdf (Page 110)

2-52 Computer Group Literature Center Web Site

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

Processor’s Current Task Priority

Each processor has a task priority register which is set by system software

to indicate the relative importance of the task running on that processor.

The processor will not receive interrupts with a priority level equal to or

lower than its current task priority. Therefore setting the current task

priority to 15 prohibits the delivery of all interrupts to the associated

processor.

Nesting of Interrupt Events

A processor is guaranteed never to have an in service interrupt preempted

by an equal or lower priority source. An interrupt is considered to be in

service from the time its vector is returned during an interrupt

acknowledge cycle until an EOI (End of Interrupt) is received for that

interrupt. The EOI cycle indicates the end of processing for the highest

priority in service interrupt.

Spurious Vector Generation

Under certain circumstances the MPIC will not have a valid vector to

return to the processor during an interrupt acknowledge cycle. In these

cases the spurious vector from the spurious vector register will be returned.

The following cases would cause a spurious vector fetch.

❏ INT is asserted in response to an externally sourced interrupt which

is activated with level sensitive logic and the asserted level is

negated before the interrupt is acknowledged.

❏ INT is asserted for an interrupt source which is masked using the

mask bit in the Vector-Priority register before the interrupt is

acknowledged.

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Motorola MVME2400 Series Manuel de service Page 110