Motorola MVME2400 Series Manuel de service télécharger pdf (Page 120)

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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

Operation

Interprocessor Interrupts

Four interprocessor interrupt (IPI) channels are provided for use by all

processors. During system initialization the IPI vector/priority registers for

each channel should be programmed to set the priority and vector returned

for each IPI event. During system operation a processor may generate an

IPI by writing a destination mask to one of the IPI dispatch registers. Note

that each IPI dispatch register is shared by both processors. Each IPI

dispatch register has two addresses but they are shared by both processors.

That is there is a total of four IPI dispatch registers in the MPIC.

The IPI mechanism may be used for self interrupts by programming the

dispatch register with the bit mask for the originating processor.

Dynamically Changing I/O Interrupt Configuration

The interrupt controller provides a mechanism for safely changing the

vector, priority, or destination of I/O interrupt sources. This is provided to

support systems which allow dynamic configuration of I/O devices. In

order to change the vector, priority, or destination of an active interrupt

source, the following sequence should be performed:

❏ Mask the source using the MASK bit in the vector/priority register.

❏ Wait for the activity bit (ACT) for that source to be cleared.

❏ Make the desired changes.

❏ Unmask the source.

This sequence ensures that the vector, priority, destination, and mask

information remain valid until all processing of pending interrupts is

complete.

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Motorola MVME2400 Series Manuel de service Page 120