Motorola MVME2400 Series Manuel de service Page 17
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
xvii
List of Tables
Table 1-1. MVME240x Features ..............................................................................1-3
Table 1-2. Default Processor Memory Map ..............................................................1-9
Table 1-3. CHRP Memory Map Example................................................................1-10
Table 1-4. PHB Register Values for CHRP Memory Map ......................................1-11
Table 1-5. PREP Memory Map Example.................................................................1-12
Table 1-6. PHB Register Values for PREP Memory Map .......................................1-13
Table 1-7. PCI CHRP Memory Map .......................................................................1-14
Table 1-8. PHB PCI Register Values for CHRP Memory Map ...............................1-16
Table 1-9. Universe II PCI Register Values for CHRP Memory Map ....................1-16
Table 1-10. PCI PREP Memory Map.......................................................................1-18
Table 1-11. PHB PCI Register Values for PREP Memory Map ..............................1-19
Table 1-12. Universe II PCI Register Values for PREP Memory Map....................1-20
Table 1-13. Universe II PCI Register Values for VMEbus Slave Map Example.....1-25
Table 1-14. VMEbus Slave Map Example...............................................................1-26
Table 1-15. 16550 Access Registers ........................................................................1-29
Table 1-16. MK48T59/559 Access Registers ..........................................................1-31
Table 1-17. VME Registers......................................................................................1-32
Table 1-18. Emulated Z8536 Access Registers........................................................1-37
Table 1-19. Z8536 CIO Port Pins Assignment ........................................................1-37
Table 2-1. PPC Slave Response Command Types ....................................................2-8
Table 2-2. PPC Master Transaction Profiles and Starting Offsets ...........................2-11
Table 2-3. PPC Master Write Posting Options.........................................................2-12
Table 2-4. PPC Master Read Ahead Options ..........................................................2-12
Table 2-5. PPC Master Transfer Types ....................................................................2-14
Table 2-6. PPC Arbiter Pin Assignments.................................................................2-15
Table 2-7. PCI Slave Response Command Types....................................................2-22
Table 2-8. PCI Master Command Codes ................................................................2-26
Table 2-9. PCI Arbiter Pin Description....................................................................2-33
Table 2-10. Fixed Mode Priority Level Setting .......................................................2-34
Table 2-11. Mixed Mode Priority Level Setting .....................................................2-35
Table 2-12. Arbitration Setting ................................................................................2-36
Table 2-13. Address Modification for Little Endian Transfers................................2-39
Table 2-14. WDTxCNTL Programming..................................................................2-43
Table 2-15. PHB Hardware Configuration ..............................................................2-48
- MVME2400-Series 1
- VME Processor Module 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- ©Copyright Motorola 1999 4
- All Rights Reserved 4
- March 1999 4
- Safety Summary 5
- Safety Depends On You 5
- Contents 7
- Glossary 14
- List of Figures 15
- List of Tables 17
- 1Board Description and 21
- Memory Maps 21
- Overview 23
- Feature Summary 23
- System Block Diagram 24
- 2067 9708 26
- Configuration 36
- PCI MEMORYPROCESSOR 42
- PCI Memory 44
- Processor 44
- ISA Space 44
- PCI I/O Space 44
- ISA Local Resource Bus 49
- VME Registers 51
- Introduction 59
- ❏ Interrupt Controller 60
- Block Diagram 61
- PPC Bus Interface 63
- ❏ HAWK (Highest Priority) 74
- ❏ CPUy (Lowest Priority) 74
- PCI Bus Interface 76
- ❏ Memory and I/O 87
- ❏ Configuration 87
- ❏ Special Cycle 87
- ❏ Interrupt Acknowledge 87
- PPC Address + Offset 88
- PCI Address 88
- 0 0 0 0 0 0 0 88
- Endian Conversion 95
- 1916 9610 96
- Error Handling 98
- Watchdog Timers 99
- PCI/PPC Contention Handling 102
- Functional Description 103
- Transaction Ordering 104
- PHB Hardware Configuration 106
- External Interrupt Interface 108
- Architecture 108
- CSR’s Readability 109
- Interrupt Source Priority 109
- Nesting of Interrupt Events 110
- Spurious Vector Generation 110
- 8259 Compatibility 111
- PHB Detected Errors 111
- Interrupt Delivery Modes 112
- Block Diagram Description 113
- Programming Notes 118
- Operation 120
- Architectural Notes 121
- Registers 123
- MBT Time Out Length 128
- 00 256 µsec 128
- 01 64 µsec 128
- 10 8 µsec 128
- 11 disabled 128
- PCI Registers 153
- $CFB $CFA $CF9 $CF8 162
- $CF8 $CF9 $CFA $CFB 162
- MPIC Registers 166
- Timer 0 - $01100 176
- Timer 0 - $01120 178
- Processor 0 $20080 184
- 3System Memory Controller 187
- Block Diagrams 188
- PowerPC 60x Bus 189
- SDRAMPowerPC 190
- Side Side 190
- PowerPC 60x Bus Interface 199
- ROM/Flash Interface 204
- I2C Interface 209
- Refresh/Scrub 221
- CSR Accesses 221
- External Register Set 221
- Chip Configuration 221
- Programming Model 222
- Table 3-9. Register Summary 223
- ERR_SYNDROME 236
- SBE_COUNT 236
- ERROR_ADDRESS 238
- I2_DATARD 252
- Software Considerations 262
- Possible Control Bit Values 266
- ECC Codes 274
- 4Universe II (VMEbus to PCI) 277
- Registers (UCSR) 283
- Universe II Register Map 284
- Register Name 285
- LSI0_TO 285
- LSI1_TO 286
- LSI2_TO 286
- LSI3_TO 286
- VSI0_TO 288
- VSI1_TO 288
- VSI2_TO 288
- VSI3_TO 288
- VCSR_TO 289
- 5Programming Details 291
- Interrupt Handling 292
- Hawk MPIC 293
- 8259 Interrupts 294
- ISA DMA Channels 297
- Exceptions 298
- Soft Reset 299
- Endian Issues 301
- Figure 5-3. Big-Endian Mode 302
- PCI Local Bus 302
- 60X System Bus 302
- Processor/Memory Domain 304
- MPIC’s Involvement 304
- PCI Domain 304
- Universe II’s Involvement 305
- VMEbus Domain 305
- ROM/Flash Initialization 306
- Ordering Related 307
- Documentation 307
- Manufacturers’ Documents 308
- Publication 309
- Document Title and Source 309
- Related Specifications 311
- MVME2400 VPD Reference 315
- Information 315
- Field Size 319
- VPD data packet 320
- Example VPD SROM 322
- Numerics 341
- 2-87, 2-89 348
- Programmer’s Reference Guide 353
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