3-1
3
3System Memory Controller
(SMC)
Introduction
The SMC in the Hawk ASIC is equivalent to the former Falcon Pair
portion of a Falcon/Raven chipset. As were its predecessors, it is designed
for the MVME family of boards. The SMC has interfaces between the
PowerPC 60x bus (also called PPC60x bus or PPC bus) and SDRAM,
ROM/Flash, and its control and status register sets (CSR). Note that the
term SDRAM refers to Synchronous Dynamic Random Access Memory
and is used throughout this document.
Overview
This chapter provides a functional description and programming model for
the SMC portion of the Hawk. Most of the information for using the device
in a system, programming it in a system, and testing it is contained here.
Bit Ordering Convention
All SMC bused signals are named using big-endian bit ordering (bit 0 is
the most significant bit), except for the RA signals, which use little-endian
bit ordering (bit 0 is the least significant bit).
Features
❏ SDRAM Interface
– Double-bit error detect/Single-bit error correct on 72-bit basis.
– Two blocks with up to 256Mbytes each at 100MHz.
– Eight blocks with up to 256Mbytes each at 66.67MHz
– Uses -8, -10, or PC100 SDRAMs
– Programmable base address for each block.
– Built-in Refresh/Scrub.
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