Motorola MVME2400 Series Manuel de service Page 222

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3-36 Computer Group Literature Center Web Site
System Memory Controller (SMC)
3
after the rising edge of the PURST_ signal pin. A recommended way to
control the RD signals during reset is to place pull-up or pull-down
resistors on the RD bus. If there is a set of buffers between the RD bus and
the ROM/Flash devices, it is best to put the pull-up/pull-down resistors on
the far side of the buffers so that loading will be kept to a minimum. The
Hawk’s SDRAM buffer control signals cause the buffers to drive toward
the Hawk during power-up reset.
Other configuration information is needed by software to properly
configure the Hawk’s control registers. This information can be obtained
from devices connected to the I2C bus.
Programming Model
CSR Architecture
The CSR (control and status register set) consists of the chip’s internal
register set and its external register set. The base address of the CSR is hard
coded to the address $FEF80000 (or $FEF90000 if the RD[5] pin is low at
reset).
Accesses to the CSR are performed on the upper 32 bits of the PPC60x
data bus. Unlike the internal register set, data for the external register set
can be writen and read on both the upper and lower halves of the PPC60x
data bus.
CSR read accesses can have a size of 1, 2, 4, or 8 bytes with any alignment.
CSR write accesses are restricted to a size of 1 or 4 bytes and they must be
aligned.
Register Summary
Table 3-9 on the following page shows a summary of the internal and
external register set.
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