Motorola MVME2400 Series Manuel de service Page 24
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Board Description and Memory Maps
1
System Block Diagram
The MVME2400 is a VMEbus-based single-slot Single Board Computer
based on the PowerPC MPC750 processor. The MVME2400 features two
PCI Mezzanine Card slots, an Ethernet Interface, serial port, up to 9MB of
boot FLASH, and up to 256MB of ECC protected system RAM. The Hawk
ASIC controls all of the functions previously controlled by the
Raven/Falcon chipsets, in addition to new functionality. The Hawk
provides the interface to the PowerPC 60x Bus, the interface to all on-
board SDRAMs, error notification for SDRAMs, the interface to
ROM/Flash, and the I2C master, the external status/control register
support, synchronous PPC60x/PCI clock ratio support, the interface to the
PCI, and an interrupt controller. PCI devices include: VME, Ethernet, and
Real-time clock 8KB NVRAM with RTC and battery backup (SGS-Thomson M48T559)
Peripheral Support
One 16C550-compatible async serial port routed to front panel RJ45
10BaseT/100BaseTX Ethernet interface routed to front panel RJ45
Switches Reset
(RST) and Abort (ABT)
Status LEDs Four: Board fail (BFL), CPU, PMC (one for PMC slot 2, one for slot 1)
Timers
One 16-bit timer in W83C553 ISA bridge; four 32-bit timers in MPIC
device
Watchdog timer provided in SGS-Thomson M48T59
VME I/O VMEbus P2 connector
Serial I/O One asynchronous debug port via RJ45 connector on front panel
Ethernet I/O 10Base-T/100Base-TX connections via RJ45 connector on front panel
PCI interface
Two IEEE P1386.1 PCI Mezzanine Card (PMC) slots for one double-
width or two single-width PMCs
Front panel and/or VMEbus P2 I/O on both PMC slots
One 114-pin Mictor connector for optional PMCspan expansion module
VMEbus interface
VMEbus system controller functions
64-bit PCI (Universe II)
VMEbus-to-local-bus interface (A32/A24/A16, D64 (MBLT)
D32//D16/D08 Master and Slave
Table 1-1. MVME240x Features (Continued)
Feature Description
- MVME2400-Series 1
- VME Processor Module 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- ©Copyright Motorola 1999 4
- All Rights Reserved 4
- March 1999 4
- Safety Summary 5
- Safety Depends On You 5
- Contents 7
- Glossary 14
- List of Figures 15
- List of Tables 17
- 1Board Description and 21
- Memory Maps 21
- Overview 23
- Feature Summary 23
- System Block Diagram 24
- 2067 9708 26
- Configuration 36
- PCI MEMORYPROCESSOR 42
- PCI Memory 44
- Processor 44
- ISA Space 44
- PCI I/O Space 44
- ISA Local Resource Bus 49
- VME Registers 51
- Introduction 59
- ❏ Interrupt Controller 60
- Block Diagram 61
- PPC Bus Interface 63
- ❏ HAWK (Highest Priority) 74
- ❏ CPUy (Lowest Priority) 74
- PCI Bus Interface 76
- ❏ Memory and I/O 87
- ❏ Configuration 87
- ❏ Special Cycle 87
- ❏ Interrupt Acknowledge 87
- PPC Address + Offset 88
- PCI Address 88
- 0 0 0 0 0 0 0 88
- Endian Conversion 95
- 1916 9610 96
- Error Handling 98
- Watchdog Timers 99
- PCI/PPC Contention Handling 102
- Functional Description 103
- Transaction Ordering 104
- PHB Hardware Configuration 106
- External Interrupt Interface 108
- Architecture 108
- CSR’s Readability 109
- Interrupt Source Priority 109
- Nesting of Interrupt Events 110
- Spurious Vector Generation 110
- 8259 Compatibility 111
- PHB Detected Errors 111
- Interrupt Delivery Modes 112
- Block Diagram Description 113
- Programming Notes 118
- Operation 120
- Architectural Notes 121
- Registers 123
- MBT Time Out Length 128
- 00 256 µsec 128
- 01 64 µsec 128
- 10 8 µsec 128
- 11 disabled 128
- PCI Registers 153
- $CFB $CFA $CF9 $CF8 162
- $CF8 $CF9 $CFA $CFB 162
- MPIC Registers 166
- Timer 0 - $01100 176
- Timer 0 - $01120 178
- Processor 0 $20080 184
- 3System Memory Controller 187
- Block Diagrams 188
- PowerPC 60x Bus 189
- SDRAMPowerPC 190
- Side Side 190
- PowerPC 60x Bus Interface 199
- ROM/Flash Interface 204
- I2C Interface 209
- Refresh/Scrub 221
- CSR Accesses 221
- External Register Set 221
- Chip Configuration 221
- Programming Model 222
- Table 3-9. Register Summary 223
- ERR_SYNDROME 236
- SBE_COUNT 236
- ERROR_ADDRESS 238
- I2_DATARD 252
- Software Considerations 262
- Possible Control Bit Values 266
- ECC Codes 274
- 4Universe II (VMEbus to PCI) 277
- Registers (UCSR) 283
- Universe II Register Map 284
- Register Name 285
- LSI0_TO 285
- LSI1_TO 286
- LSI2_TO 286
- LSI3_TO 286
- VSI0_TO 288
- VSI1_TO 288
- VSI2_TO 288
- VSI3_TO 288
- VCSR_TO 289
- 5Programming Details 291
- Interrupt Handling 292
- Hawk MPIC 293
- 8259 Interrupts 294
- ISA DMA Channels 297
- Exceptions 298
- Soft Reset 299
- Endian Issues 301
- Figure 5-3. Big-Endian Mode 302
- PCI Local Bus 302
- 60X System Bus 302
- Processor/Memory Domain 304
- MPIC’s Involvement 304
- PCI Domain 304
- Universe II’s Involvement 305
- VMEbus Domain 305
- ROM/Flash Initialization 306
- Ordering Related 307
- Documentation 307
- Manufacturers’ Documents 308
- Publication 309
- Document Title and Source 309
- Related Specifications 311
- MVME2400 VPD Reference 315
- Information 315
- Field Size 319
- VPD data packet 320
- Example VPD SROM 322
- Numerics 341
- 2-87, 2-89 348
- Programmer’s Reference Guide 353
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