Motorola MVME2400 Series Manuel de service Page 283

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Registers - Universe II Control and Status Registers (UCSR)
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4
DMA Controller
The Universe II provides an internal DMA controller for high performance
data transfer between the PCI and VMEbus. DMA operations between the
source and destination bus are decoupled through the use of a single
bidirectional FIFO (DMAFIFO). Parameters for the DMA transfer are
software configurable in the Universe II registers. (Refer to DMA
Controller in the Universe II User Manual.)
The principal mechanism for DMA transfers is the same for operations in
either direction (PCI to VME, or VME to PCI), only the relative identity
of the source and destination bus changes. In a DMA transfer, the
Universe II gains control of the source bus and reads data into its
DMAFIFO. Following specific rules of DMAFIFO operation (refer to
FIFO Operation and Bus Ownership in the Universe II User Manual), it
then acquires the destination bus and writes data from its DMAFIFO.
The DMA controller can be programmed to perform multiple blocks of
transfers using entries in a linked list. The DMA will work through the
transfers in the linked-list following pointers at the end of each linked-list
entry. Linked-list operation is initiated through a pointer in an internal
Universe II register, but the linked list itself resides in PCI bus memory.
Registers - Universe II Control and Status
Registers (UCSR)
The Universe II Control and Status Registers (UCSR) facilitate host
system configuration and allow the user to control Universe II operational
characteristics. The UCSRs are divided into three groups:
PCI Configuration Space (PCICS)
VMEbus Control and Status Registers (VCSR), and
Universe II Device Specific Status Registers (UDSR)
The Universe II registers are little-endian.
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