Motorola MVME2400 Series Manuel de service télécharger pdf (Page 341)

IN-1

Index

Numerics

16550 access registers 1-29

16550 UART 1-29

32-Bit Counter 3-73

SMC 3-73

8259 interrupts

PIB 5-4

A

A0-A31 3-5

AACK

as used with PPC Slave 2-7

abbreviations, acronyms, and terms to know

GL-1

access timing (ROM) 3-11, 3-12

address

decoders PPC to PCI 2-7

limits on PHB map decoding 2-6

address decoders

PCI to PPC 2-5

address mapping

PPC 2-5

address modification for little endian trans-

fers 2-39

address offsets

as part of map decoders 2-20

address parity

PPC60x 3-15

Address Parity Error Address Register

SMC 3-72

Address Parity Error Log Register

SMC 3-71

address pipelining 3-7

address transfers 3-13

address/data stepping 2-28

addressing

to PCI Slave 2-22

addressing mode

for PCI Master 2-27

PCI Slave limits 2-23

Application-Specific Integrated Circuit

(ASIC) 1-1

arbiter

as controlled by the XARB register 2-16

Hawk’s internal 2-33

PPC 2-14, 2-16

arbitration

from PCI Master 2-28

arbitration latency 2-28

arbitration parking 2-36

architectural diagram for the Universe 4-3

architectural overview 2-4

Universe II 4-2

ARTRY_ 3-15

assertion, definition 1-2

asterisk (*)

as denotes signal level 1-2

B

big to little endian data swap 2-38

big-endian 1-2

big-endian mode 5-12

binary number 1-1

bit descriptions 3-39

bit ordering convention

SMC 3-1

1 2 ... 336 337 338 339 340 341 342 343 344 345 346 ... 353 354

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