Motorola MVME2400 Series Manuel de service Page 74

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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
2
HAWK (Highest Priority)
EXTL
CPUx
CPUy (Lowest Priority)
The PPC Arbiter is controlled by the XARB register within the PHB
PPC60x register group.
The PPC Arbiter supports two prioritization schemes. Both schemes affect
the priority of the CPU’s with respect to each other. The CPU fixed option
always places the priority of CPU0 over that of CPU1. The CPU rotating
option gives priority on a rotational basis between CPU0 and CPU1. In all
cases the priority of the CPUs remains fixed with respect to the priority of
HAWK and EXTL, with HAWK always having the highest priority of all.
The PPC Arbiter supports four parking modes. Parking is implemented
only on the CPUs and is not implemented on either HAWK or EXTL. The
parking options include parking on CPU0, parking on CPU1, parking on
the last CPU, or parking disabled.
There are various system level debug functions provided by the PPC
Arbiter. The PPC Arbiter has the optional ability to flatten the PPC60x bus
pipeline. Flattening can be imposed uniquely on single beat reads, single
beat writes, burst reads, and burst writes. It is possible to further qualify the
ability to flatten based on whether there is a switch in masters or whether
to flatten unconditionally for each transfer type. This is a debug function
only and is not intended for normal operation.
PPC Parity
PHB will generate data parity whenever it is sourcing PPC data. This
happens during PPC Master write cycles and PPC Slave read cycles. Valid
data parity will be presented when DBB_ is asserted for PPC Master write
cycles. Valid data parity will be presented when TA_ is asserted for PPC
Slave read cycles.
PHB will check data parity whenever it is sinking PPC data. This happens
during PPC Master read cycles and PPC Slave write cycles. Data parity
will be considered valid anytime TA_ has been asserted. If a data parity
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