Motorola MVME2400 Series Manuel de service télécharger pdf (Page 76)

2-18 Computer Group Literature Center Web Site

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller

If the transaction was an address only cycle, then no further action will be

taken. If the faulty transaction was a data transfer cycle, then the PPC

Timer will assert the appropriate number of TA_’s to close the pending

data tenure. Error information related to the faulty transaction will be

latched within the ESTAT, EADDR, and EATTR registers, and an

interrupt or machine check will be generated depending on the

programming of the ESTAT register.

There are two exceptions that will dynamically disable the PPC Timer. If

the transaction is PCI bound, then the burden of closing out a transaction

is left to the PCI bus. Note that a transaction to the PPC60x registers is

considered to be PCI bound since the completion of these types of accesses

depends on the ability of the PCI bus to empty PCI bound write posted

data.

A second exception is the assertion of the XBTCLM_ signal. This is an open

collector (wired OR) bi-directional signal that is used by a bridge to indicate the

burden of timing a transaction has been passed on to another bus domain. The

PHB will assert this signal whenever it has determined that a transaction is being

timed by its own PCI bus. Any other bridge devices listening to this signal will

understand that the current pending cycle should not be subject to a time-out

period. During non-PCI bound cycles, PPC Timer will abort the timing of the

transaction any time it detects XBTCLM_ has been asserted

PCI Interface.

PCI Bus Interface

The PCI Interface of the PHB is designed to connect directly to a PCI

Local Bus and supports Master and Target transactions within Memory

Space, I/O Space, and Configuration Space.

PCI Address Mapping

The PHB provides three resources to the PCI:

❏ Configuration registers mapped into PCI Configuration space

❏ PPC bus address space mapped into PCI Memory space

❏ MPIC control registers mapped into either PCI I/O space or PCI

Memory space

1 2 ... 71 72 73 74 75 76 77 78 79 80 81 ... 353 354

Pas de commentaire

Motorola MVME2400 Series Manuel de service Page 76