Motorola D512 Spécifications

1 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Mobile DiskOnChip G3 512Mbit/1Gbit Flash Disk with MLC NAND and M-Systems’ x2 Technology Pre

Mobile DiskOnChip G3 7 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2. PRODUCT OVERVIEW 2.1 Product Description Mobile DiskOnChip G3 is the la

Mobile DiskOnChip G3 8 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.2 512Mb Standard Interface 2.2.1 Pin/Ball Diagrams See Figure 1 and Fig

Mobile DiskOnChip G3 9 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7x10 FBGA Package MABCDEFGHJKLM1 2 3 4 5 6 7 8MM MA7A RSRVD RSRVD WE# A8 A

Mobile DiskOnChip G3 10 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.2.2 System Interface See Figure 3 for a simplified I/O diagram for a st

Mobile DiskOnChip G3 11 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.2.3 Signal Description Mobile DiskOnChip G3 TSOP-I and FBGA packages su

Mobile DiskOnChip G3 12 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Signal Pin No. Input Type Description Signal Type DMARQ# 21 OD DMA Reques

Mobile DiskOnChip G3 13 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7x10 FBGA Package Table 2: Signal Descriptions for Standard Interface (Mo

Mobile DiskOnChip G3 14 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Signal Ball No. Input Type Description Signal Type IRQ# F8 OD Interrupt R

Mobile DiskOnChip G3 15 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.3 1Gb Standard Interface 2.3.1 Ball Diagram See Figure 4 for the Mobil

Mobile DiskOnChip G3 16 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.3.2 System Interface See Figure 5 for a simplified I/O diagram for a st

Mobile DiskOnChip G3 2 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Performance  MultiBurst read: 80 MB/sec  Erase: 30 MB/sec  Sustained

Mobile DiskOnChip G3 17 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.3.3 Signal Description 9x12 FBGA Package Table 3: Signal Descriptions f

Mobile DiskOnChip G3 18 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Signal Ball No. Input Type Description Signal Type IRQ# F9 OD Interrupt R

Mobile DiskOnChip G3 19 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.4 512Mb Multiplexed Interface 2.4.1 Pin/Ball Diagram See Figure 6 and

Mobile DiskOnChip G3 20 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7x10 FBGA Package MABCDEFGHJKLM1 2 3 4 5 6 7 8MM MVSSA RSRVD RSRVD WE# VS

Mobile DiskOnChip G3 21 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.4.2 System Interface See Figure 8 for a simplified I/O diagram. MobileD

Mobile DiskOnChip G3 22 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.4.3 Signal Description Mobile DiskOnChip G3 512Mb TSOP-I and 7x10 FBGA

Mobile DiskOnChip G3 23 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Signal Pin No. Input Type Description Signal Type Power VCCQ 37,22 - I

Mobile DiskOnChip G3 24 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7x10 FBGA Package Table 5: Signal Descriptions for Multiplexed Interface

Mobile DiskOnChip G3 25 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Signal Ball No. Input Type Description Signal Type Power VCC J4 - De

Mobile DiskOnChip G3 26 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.5 1Gb Multiplexed Interface 2.5.1 Ball Diagram See Figure 9 for the Mo

Mobile DiskOnChip G3 3 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L TrueFFS® Software  Full hard-disk read/write emulation for transparent f

Mobile DiskOnChip G3 27 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.5.2 System Interface See Figure 10 for a simplified I/O diagram. Mobi l

Mobile DiskOnChip G3 28 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2.5.3 Signal Description 9x12 FBGA Package Table 6: Signal Descriptions f

Mobile DiskOnChip G3 29 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Signal Ball No. Input Type Description Signal Type Power VCC J5 - De

Mobile DiskOnChip G3 30 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 3. THEORY OF OPERATION 3.1 Overview Mobile DiskOnChip G3 consists of the

Mobile DiskOnChip G3 31 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L • Flash Interface that interfaces to two NAND flash planes. • Bus Contr

Mobile DiskOnChip G3 32 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L values are 0 and 1; therefore, only up to two Mobile DiskOnChip G3 512Mb

Mobile DiskOnChip G3 33 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 3.4.2 Unique Identification (UID) Number Each Mobile DiskOnChip G3 is as

Mobile DiskOnChip G3 34 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2. The Programmable Boot Block size available for Mobile DiskOnChip G3 1

Mobile DiskOnChip G3 35 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 3.9 Control and Status The Control and Status block contains registers re

Mobile DiskOnChip G3 36 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L concurrently read or written if they have the same offset within their re

Mobile DiskOnChip G3 1 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L REVISION HISTORY Revision Date Description Reference Updated RSRVD signa

Mobile DiskOnChip G3 37 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 4. X2 TECHNOLOGY Mobile DiskOnChip G3 enhances performance using various

Mobile DiskOnChip G3 38 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Flash PlaneWORD0Flash PlaneWORD132-bit Data Mux16-bit toHost16-bit Data16

Mobile DiskOnChip G3 39 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L The LATENCY bit is the third bit that must be set in the MultiBurst Mode

Mobile DiskOnChip G3 40 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 2. Set the bits in the Interrupt Control register (see Section 7) to ena

Mobile DiskOnChip G3 41 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 5. HARDWARE PROTECTION 5.1 Method of Operation Mobile DiskOnChip G3 enab

Mobile DiskOnChip G3 42 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 5.2 Low-Level Structure of the Protected Area The first five blocks in Mo

Mobile DiskOnChip G3 43 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Block 3 and 4 o Data Protect Structure 1. This structure contains config

Mobile DiskOnChip G3 44 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 6. MODES OF OPERATION Mobile DiskOnChip G3 operates in one of three basic

Mobile DiskOnChip G3 45 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 6.1 Normal Mode This is the mode in which standard operations involving t

Mobile DiskOnChip G3 46 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L • Toggle the DPD input as defined by the DPD Control register. Applicat

Mobile DiskOnChip G3 2 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L TABLE OF CONTENTS 1. Introduction ...

Mobile DiskOnChip G3 47 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L • Implementation of MLC-tailored EDC/ECC • Performance optimization •

Mobile DiskOnChip G3 48 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L In a typical application, and especially if a file system is used, specif

Mobile DiskOnChip G3 49 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 6.4.8 Error Detection/Correction TrueFFS implements a unique MLC-tailored

Mobile DiskOnChip G3 50 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Programmable Boot Block Reset ModeFlash area window (+ aliases) 000H8

Mobile DiskOnChip G3 51 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7. REGISTER DESCRIPTIONS This section describes various Mobile DiskOnChip

Mobile DiskOnChip G3 52 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.3 No Operation (NOP) Register Description: A call to this 16-bit regi

Mobile DiskOnChip G3 53 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.6 Bus Lock Register Description: This register provides a mechanism f

Mobile DiskOnChip G3 54 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.7 Endian Control Register Description: This 16-bit register is used t

Mobile DiskOnChip G3 55 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.8 DiskOnChip Control Register/Control Confirmation Register Descriptio

Mobile DiskOnChip G3 56 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.9 Device ID Select Register Description: In a cascaded configuration,

Mobile DiskOnChip G3 3 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 3.8 Data Pipeline ...

Mobile DiskOnChip G3 57 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.11 Interrupt Control Register Description: This 16-bit register contr

Mobile DiskOnChip G3 58 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Bit No. Description 14 EDGE. Selects edge or level triggered interrupts

Mobile DiskOnChip G3 59 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.13 Output Control Register Description: This register controls the be

Mobile DiskOnChip G3 60 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.14 DPD Control Register Description: This register specifies the beha

Mobile DiskOnChip G3 61 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.15 DMA Control Register [1:0] Description: These two 16-bit registers

Mobile DiskOnChip G3 62 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L DMA Control Register [1] Bits 15-10 Bits 9-0 Read/Write R R/W Descrip

Mobile DiskOnChip G3 63 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.16 MultiBurst Mode Control Register Description: This 16-bit register

Mobile DiskOnChip G3 64 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 8. BOOTING FROM MOBILE DISKONCHIP G3 8.1 Introduction Mobile DiskOnChip G

Mobile DiskOnChip G3 65 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L or the autoexec.bat/config.sys files. Mobile DiskOnChip G3 can be used as

Mobile DiskOnChip G3 66 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 8.3.2 Non-PC Architectures In non-PC architectures, the boot code is exec

Mobile DiskOnChip G3 4 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 7.8 DiskOnChip Control Register/Control Confirmation Register ...

Mobile DiskOnChip G3 67 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 9. DESIGN CONSIDERATIONS 9.1 General Guidelines A typical RISC processor

Mobile DiskOnChip G3 68 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Figure 21: Typical System Architecture Using Mobile DiskOnChip G3 9.2 Sta

Mobile DiskOnChip G3 69 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 9.3 Multiplexed Interface With a multiplexed interface, Mobile DiskOnChip

Mobile DiskOnChip G3 70 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L • Chip Identification (ID[1:0]) – Connect these signals as shown in Figu

Mobile DiskOnChip G3 71 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 9.5 Implementing the Interrupt Mechanism 9.5.1 Hardware Configuration To

Mobile DiskOnChip G3 72 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 9.6 Device Cascading When connecting Mobile DiskOnChip G3 512Mb using a s

Mobile DiskOnChip G3 73 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 9.7 Boot Replacement A typical RISC architecture uses a boot ROM for syst

Mobile DiskOnChip G3 74 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 9.8 Platform-Specific Issues This section discusses hardware design issue

Mobile DiskOnChip G3 75 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 8-Bit (Byte) Data Access Mode When configured for 8-bit operation, pin/ba

Mobile DiskOnChip G3 76 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 9.9 Design Environment Mobile DiskOnChip G3 provides a complete design en

Mobile DiskOnChip G3 5 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10. Product Specifications ...

Mobile DiskOnChip G3 77 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10. PRODUCT SPECIFICATIONS 10.1 Environmental Specifications 10.1.1 Opera

Mobile DiskOnChip G3 78 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.2.2 Capacitance Table 11: Capacitance Symbol Parameter Conditions Min

Mobile DiskOnChip G3 79 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Table 13: DC Characteristics, VCCQ = 2.5V-3.6V Symbol Parameter Conditio

Mobile DiskOnChip G3 80 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.2.4 AC Operating Conditions Timing specifications are based on the co

Mobile DiskOnChip G3 81 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.3 Timing Specifications 10.3.1 Read Cycle Timing Standard Interface

Mobile DiskOnChip G3 82 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L Table 15: Standard Interface Read Cycle Timing Parameters VCCQ=VCC VCC=2

Mobile DiskOnChip G3 83 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.3.2 Write Cycle Timing Standard Interface CE# A[12:0] tREC(WE) tHO(C

Mobile DiskOnChip G3 84 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.3.3 Read Cycle Timing Multiplexed Interface CE# AD[15:0] tREC(OE) tH

Mobile DiskOnChip G3 85 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.3.4 Write Cycle Timing Multiplexed Interface CE# tREC(WE) tHO(CE1) t

Mobile DiskOnChip G3 86 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.3.5 Read Cycle Timing MultiBurst In Figure 32, the MultiBurst Control

Mobile DiskOnChip G3 6 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 1. INTRODUCTION This data sheet includes the following sections: Section 1

Mobile DiskOnChip G3 87 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L VCCQ=VCC VCC=2.5-3.6V VCCQ=1.65-2.0V VCC=2.5-3.6V Symbol Description Mi

Mobile DiskOnChip G3 88 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L RSTIN#VCCBUSY#VCC = 2.5V VCCQ = 1.65 or 2.5V TP(BUSY1) TREC(VCC-RSTIN)CE#

Mobile DiskOnChip G3 89 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.3.8 Interrupt Timing IRQ#Tw(IRQ#) Figure 34: IRQ# Pulse Width in Edge

Mobile DiskOnChip G3 90 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.4 Mechanical Dimensions 10.4.1 Mobile DiskOnChip G3 512Mb TSOP-I dime

Mobile DiskOnChip G3 91 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L FBGA dimensions: 7.0±0.20 mm x 10.0±0.20 mm x 1.1±0.1 mm Ball pitch:

Mobile DiskOnChip G3 92 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 10.4.2 Mobile DiskOnChip G3 1Gb (Dual-Die) FBGA dimensions: 9.0±0.20 mm

Mobile DiskOnChip G3 93 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L 11. ORDERING INFORMATION MDxxxx-Dxxx-xxx-T-CDevice Code:4811 - D iskOnC h

Mobile DiskOnChip G3 94 Preliminary Data Sheet, Rev. 1.1 91-SR-011-05-8L HOW TO CONTACT US USA M-Systems Inc. 8371 Central Ave, Suite A Newark CA