Motorola NNTN5565A Manuel

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12090 South Memorial Parkway
Huntsville, Alabama 35803-3308, USA
(256) 880-0444
w (800) 322-3616 w Fax: (256) 882-0859
VMIVME-5565
Ultrahigh-Speed Fiber-Optic
Reflective Memory with Interrupts
Product Manual
500-005565-000 Rev. A
Vue de la page 0
1 2 3 4 5 6 ... 87 88

Résumé du contenu

Page 1 - VMIVME-5565

12090 South Memorial ParkwayHuntsville, Alabama 35803-3308, USA(256) 880-0444 w (800) 322-3616 w Fax: (256) 882-0859VMIVME-5565Ultrahigh-Speed Fib

Page 2 - (256) 880-0444

VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts10

Page 3 - All Rights Reserved

11List of TablesTable 1-1 VMEbus Byte Assignment to the Data Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 4

VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts12

Page 5 - Table of Contents

13OverviewContentsSpecification Compliances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Reference

Page 6

VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts14Specification Compliances VMEbus ComplianceThe VMIVME-5565 complies with re

Page 7

Overview15Figure 1 VMIVME-5565 Block DiagramReflective MemoryNetworkRXTXReflective Memory Circuitryand Transceivers66 MHz32-BitSDRAMData Bus64 or 12

Page 8

VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts16Figure 2 Typical Reflective Memory NetworkNODE 2VMEbus ComputerNodes can b

Page 9 - List of Figures

Overview17Reference Material ListFor a detailed description of the VMEbus, refer to The VMEbus Specification and Handbook available from:VMEbus Intern

Page 10

VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts18Safety SummaryThe following general safety precautions must be observed dur

Page 11 - List of Tables

Overview19Safety Symbols Used in This ManualSTOP: This symbol informs the operator the that a practice or procedure should not be performed. Actions c

Page 12

12090 South Memorial ParkwayHuntsville, Alabama 35803-3308, USA(256) 880-0444 w (800) 322-3616 w Fax: (256) 882-0859

Page 13 - Overview

VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts20

Page 14 - Specification Compliances

21CHAPTERTheory of OperationContentsBasic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 15

22 1 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsBasic OperationEach node (VMIxxx-5565 Reflective Memory boards) in t

Page 16

23VMIVME-5565 Register Sets 1VMIVME-5565 Register Sets To go beyond the simple read and write operation of the board, the user must understand and man

Page 17 - Reference Material List

24 1 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsReflective Memory RAMThe actual on-board Reflective Memory SDRAM is

Page 18 - Safety Summary

25Interrupt Circuits 1Interrupt CircuitsThe VMIVME-5565 has a single programmable VMEbus interrupt output. One or more events on the VMIVME-5565 can c

Page 19

26 1 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsFigure 1-1 VMIVME-5565 Interrupt Circuitry Block DiagramNetworkRece

Page 20

27Interrupt Circuits 1Network InterruptsThe VMIVME-5565 has the capability of passing interrupt packets over the network in addition to data. The netw

Page 21 - Theory of Operation

28 1 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsRedundant Transfer Mode of OperationThe VMIVME-5565 is capable of op

Page 22 - Basic Operation

29Byte Ordering: Big Endian / Little Endian 1Byte Ordering: Big Endian / Little EndianThe byte-ordering issue exists due to the different traditions a

Page 23 - VMIVME-5565 Register Sets

© Copyright 2002. The information in this document has been carefully checked and is believed to be entirely reliable.While all reasonable efforts to

Page 24 - Reflective Memory RAM

30 1 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts Figure 1-3 Byte Relationships Using the Big Endian 68040 Micropr

Page 25 - Interrupt Circuits

31Byte Ordering: Big Endian / Little Endian 1Endian Conversion HardwareThe Universe II chip performs Address Invariant translation between the PCI and

Page 26 - Universe II Registers

32 1 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts

Page 27 - Network Interrupts

33CHAPTERConfiguration and InstallationContentsUnpacking Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 28 - Rogue Packet Remove Operation

34 2 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsUnpacking ProceduresCAUTION: Some of the components assembled on VMI

Page 29 - Lword (32-bit) Transfer

35Unpacking Procedures 2Figure 2-1 VMIVME-5565 Location of User Configurable Switches and JumpersPos 1 = A24Pos 2 = A25Pos 3 = A26Pos 4 = A27Pos 5 =

Page 30

36 2 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsSwitch/Jumper Configuration and LocationNode ID SwitchPrior to insta

Page 31 - Endian Conversion Hardware

37Switch/Jumper Configuration and Location 2Jumper E5 Redundant Mode ConfigurationJumper E5 is used to configure the VMIVME-5565 for redundant or non-

Page 32

38 2 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsRegisters and Memory Configuration SwitchesThe VMIVME-5565 occupies

Page 33 - Contents

39Registers and Memory Configuration Switches 2CSR Address Space/Access Select Switches (S7, S4 and S3)The following switches are used to configure th

Page 34 - Unpacking Procedures

12090 South Memorial ParkwayHuntsville, Alabama 35803-3308, USA(256) 880-0444 w (800) 322-3616 w Fax: (256) 882-0859

Page 35 - Unpacking Procedures 2

40 2 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsMemory Address/Access Select Switch (S8)Switch S8 is used to configu

Page 36 - Node ID Switch

41Registers and Memory Configuration Switches 2Example 1: Register and Memory SelectThe Control and Status Registers are mapped at Standard Address $0

Page 37 - (Redundant Mode)

42 2 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsExample 2: Register and Memory SelectThe Control and Status Register

Page 38

43Registers and Memory Configuration Switches 2Example 3: Register and Memory SelectThe Control and Status Registers are mapped at Extended Address $7

Page 39

44 2 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsPhysical InstallationCAUTION: Do not install or remove the board whi

Page 40

45Front Panel Description 2Front Panel DescriptionThe VMIVME-5565 has an optical transceiver located on the front panel. Figure 2-7 below is an illust

Page 41

46 2 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsCable ConfigurationThe VMIVME-5565 is available with a multimode or

Page 42

47VMIVME-5565 Connectivity 2VMIVME-5565 ConnectivityFigure 2-9 Example: Six Node Ring ConnectivityVMIVME5565VMIVME5565VMIVMEVMIVME55655565VMIVME5565V

Page 43

48 2 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts

Page 44 - Physical Installation

49CHAPTERProgrammingContentsRFM Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50RFM Netwo

Page 45 - Front Panel Description

5Table of ContentsList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 46 - Cable Configuration

50 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsRFM Control and Status RegistersThe RFM Control and Status registers f

Page 47 - VMIVME-5565 Connectivity

51RFM Control and Status Registers 3Node ID RegisterNode ID (NID) (Offset $4): An 8-bit register containing the node ID of the board. This register re

Page 48

52 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsLocal Control and Status Register Bit Definitions (Continued)Bit 27:

Page 49 - Programming

53RFM Control and Status Registers 3Local Control and Status Register Bit Definitions (Concluded)Bit 06: TX FIFO Almost Full – A logic high (1) indi

Page 50 - Board ID Register

54 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsLocal Interrupt Control Registers (LISR and LIER)The VMIVME-5565 conta

Page 51 - Node ID Register

55RFM Control and Status Registers 3Local Interrupt Status Register Bit Definitions (Continued)Bit 13: Local Memory Parity Error – When this bit is h

Page 52 - Config 1 Config 0 Memory Size

56 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsLocal Interrupt Status Register Bit Definitions (Concluded)NOTE: Readi

Page 53

57RFM Network Registers 3RFM Network RegistersThe NTD, NTN and the NIC registers described below are involved with the generation of network interrupt

Page 54

58 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsInterrupt 1 Sender ID FIFOEach time one node issues a network interrup

Page 55

59RFM Network Registers 3Interrupt 4 Sender Data FIFOThe Interrupt 4 Sender Data (ISD4) FIFO is located at offset $38 and functions just like ISD1, ex

Page 56

VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts6Byte Ordering: Big Endian / Little Endian . . . . . . . . . . . . . . . . .

Page 57 - RFM Network Registers

60 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsExample of Network Interrupt Handling The following is an example of t

Page 58

61Example of Network Interrupt Handling 3Servicing Network Interrupts:1. Read LISR register at RFMCSRBase + offset $10. Determine if the pending Netw

Page 59 - Interrupt 4 Sender Data FIFO

62 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsUniverse II RegistersThe Universe II registers facilitate host system

Page 60 - Interrupt Setup Routine:

63Universe II Control and Status Registers 3Universe II Control and Status RegistersVMEbus Interrupt Enable Register (VINT_EN)This register enables th

Page 61 - Servicing Network Interrupts:

64 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsVMEbus Interrupt Enable Register Bit Definitions (Cont.)Bit 29: SW_INT

Page 62

65Universe II Control and Status Registers 3VMEbus Interrupt Enable Register Bit Definitions (Concluded)Bit 16: MBOX0 (Read/Write): Mailbox 0 Mask 0 =

Page 63 - Reserved LINT0

66 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsVMEbus Interrupt Status Register (VINT_STAT)SW_INT can be set with the

Page 64

67Universe II Control and Status Registers 3VMEbus Interrupt Status Register Bit Definitions (Cont.)Bit 19: MBOX3 (Read/Write 1 to clear): Mailbox 3 S

Page 65

68 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsVME Interrupt Map 0 Register (VINT_MAP0)This register maps various int

Page 66

69Universe II Control and Status Registers 3VME Interrupt Map 1 Register (VINT_MAP1)This register maps various interrupt sources to one of the seven V

Page 67

Table of Contents7Interrupt 4 Sender ID FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Page 68 - Reserved

70 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsInterrupt Status/ID Out Register (STATID)When the Universe II responds

Page 69 - Reserved LERR Reserved DMA

71Universe II DMA Registers 3Universe II DMA RegistersThe Universe II has a DMA controller for high performance data transfer between the RFM and VMEb

Page 70 - STATID [7:0] Reserved

72 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsDMA Transfer Control Register Bit Definitions (Cont.)Bits 21 thru 19:

Page 71 - Universe II DMA Registers

73Universe II DMA Registers 3DMA PCI Bus Address Register (DLA)This register is programmed from either bus or by the DMA Controller when it loads a co

Page 72

74 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsDMA VMEbus Address Register (DVA)This register is programmed from eith

Page 73 - $208, Read/Write

75Universe II DMA Registers 3DMA Command Packet Pointer (DCPP)This register contains the pointer into the current command packet. Initially it is prog

Page 74

76 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsDMA General Control and Status Register (DGCS)The DMA General Control

Page 75 - DCPP Reserved

77Universe II DMA Registers 3DMA General Control and Status Register Bit Definitions (Cont.)Bit 15: ACT (Read Only): DMA Active Status Bit, 0 = Not Ac

Page 76 - Reserved VON VOFF

78 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsMailbox 0 Register (MBOX0)Mailbox 0 Bit DefinitionsBits 31 thru 00: MB

Page 77 - Universe II DMA Registers 3

79DMA Source and Destination Addresses 3DMA Source and Destination AddressesThe source and destination addresses for the DMA reside in two registers:

Page 78 - Mailbox 2 Bit Definitions

VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts8

Page 79 - Transfer Size

80 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsThe DTBC register is not updated while the DMA is active (indicated by

Page 80 - Transfer Data Width

81DMA Source and Destination Addresses 3DMA Command Packet PointerThe DMA Command Packet Pointer (DCPP in Table 3-16 on page 75) points to a 32-byte a

Page 81 - DMA VMEbus Ownership

82 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts1K, 2K, 4K, 8K, or 16K). When performing MBLT transfers on the VMEbus,

Page 82

83DMA Source and Destination Addresses 3After a stop or halt, the DMA can be restarted from the point it left off by setting the GO bit; but before it

Page 83

84 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsDMA Transfer OperationThe Universe II DMA is set through manual regist

Page 84 - DMA Transfer Operation

85DMA Source and Destination Addresses 3In Step 1, the DGCS register is set up: the CHAIN bit is cleared, VON and VOFF are programmed with the appropr

Page 85

86 3 VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with InterruptsIf the DONE bit was set, it indicates that the DMA completed its reque

Page 86 - . This is the

87MaintenanceMaintenanceThis section provides information relative to the care and maintenance of VMIC’s products. If the product malfunctions, verify

Page 87 - Maintenance

VMIVME-5565 Ultrahigh-Speed Fiber-Optic Reflective Memory with Interrupts88Maintenance PrintsUser level repairs are not recommended. The drawings and

Page 88 - Maintenance Prints

9List of FiguresFigure 1 VMIVME-5565 Block Diagram ........................

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