MC68332TUT/D MOTOROLA
13
Figure 8 Typical MC68332 Reset Circuit
When the internal PLL is used to generate the internal system clock, the RESET pin works as follows. At
power-up, the MCU drives RESET low. When the PLL locks, the MCU releases RESET for two system clock
cycles. If the external pull-up resistor can pull RESET to a logic 1 during the two cycles, the MCU assumes
that the reset is a power-on reset, rather than an external reset. However, if RESET does not rise to a logic
1 during the two cycles, the MCU assumes that the reset is an external reset and drives RESET to a logic
0 for 512 clock cycles. After 512 cycles have elapsed, the MCU releases RESET for 10 clock cycles. If RE-
SET is a logic 1 at the end of the 10 cycles, the MCU begins program execution. If RESET is a logic 0 at
the end of the 10 cycles, the MCU once again actively drives RESET low for 512 clock cycles. This cycle
repeats until RESET is finally perceived to be at a logic 1. Figure 9 shows the waveform that is produced
on the RESET line when the pull-up resistor is too large and pull-up current is inadequate.
Figure 9 RESET
Waveform Caused By Weak Pull-Up
If the PLL circuit is not used, and an external clock at the desired frequency of the system clock is applied
to EXTAL prior to start-up, the start up sequence is the same except that the MCU recognizes the clock
immediately instead of waiting for the PLL to lock.
332TUT LVI/RESET CONN
RESET
O.C.
MC68332
LOW VOLTAGE
INHIBIT DEVICE
+5V
10KΩ 820Ω
10–100µF
+5V +5V
332TUT RESET LEVEL TIM
0 VOLTS
5 VOLTS
INDETERMINATE
LOGIC LEVEL
512 SYSTEM CLOCKS
10 OR 14 SYSTEM CLOCKS
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