Motorola M68CPU32BUG Manuel d'utilisateur télécharger pdf (Page 17)

MC68332TUT/D MOTOROLA

Another way to control power supply noise created by the MCU is to put a small inductor in series with the

power supply lines for the port drivers. This method can help control noise on the power traces of the PCB.

However, it should be used only as a last resort, because it can introduce other noise problems. Also, a

series inductor in the power supply line will probably have little effect on radiated noise, which is generally

a result of the port driver switching speed. Limiting instantaneous current change by putting an inductor in

series with the power supply pin for the port will not appreciably affect the current through a particular driver,

because the integrated circuit generally has enough internal capacitance to support an instantaneous cur-

rent surge while the driver switches.

Figure 12 Proper Placement of a Bypass Capacitor

The V

DDSYN

and V

STBY

supply pins should be separated and isolated from V

with a low pass filter. Any

supply noise present on V

DDSYN

will translate into shifts in the system clock generated from the PLL. Always

supply power to V

DDSYN

, even when using an external oscillator and bypassing the internal PLL.

2.8.2 A Few Suggestions for Reducing Emissions

In general, follow standard design practices for EMC. A list of techniques that are often used in board design

follows. These techniques are guidelines for good design, not strict rules, and are not specific to designs

that incorporate the MC68332.

• Minimize the number of devices on the board. Capacitive coupling tends to occur around the holes

that connect a particular layer of the board to the power and ground planes.

• Use a canned oscillator instead of a crystal, to reduce emissions from the oscillator. If a crystal circuit

must be used, locate it as centrally as possible.

• Use a four layer PCB. As a general rule, a multilayer board is at least10 times better than a two layer

board for both emissions and immunity. To reduce emissions even further, enclose the signal traces

between the power and ground planes because the added capacitance between the signal trace and

ground results in a lower characteristic impedance.

• Plot thick layout lines with the layout program, then cut the actual traces on the board thin.

• If a trace that conducts a high frequency signal must be routed on the surface of the PCB, route ground

traces parallel to it to reduce radiation and crosstalk. Connect the ground traces to ground planes at

varied intervals not to exceed the wavelength/4 at the highest frequency or harmonic expected.

• Round off PCB trace corners as much as possible to reduce the amount of excess capacitance that

is introduced to the trace at corners.

• Make spacing between adjacent active traces greater than the trace width to minimize crosstalk.

• Put a chassis ground ring on the periphery of each layer of the PCB, to intercept the field coming off

the board. Interconnect these rings with small ceramic capacitors.

332TUT VDD LAYOUT

GND PLANE

POWER PLANE

BYPASS

CAP

VDD PIN

(.1 µF TYPICAL)

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 55 56

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Motorola M68CPU32BUG Manuel d'utilisateur Page 17

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