Motorola M68CPU32BUG Manuel d'utilisateur télécharger pdf (Page 22)

MOTOROLA MC68332TUT/D

Figure 15 Configuring 16-Bit Memory with 8-Bit RAMs — Separate Read and Write Enables

2.10 Using External Interrupts

The MCU has seven external interrupt lines, IRQ[7:1]. These are active low signals that cause the processor

to jump to a special routine and then return to the main code. The following paragraphs cover the basic el-

ements of servicing external interrupt service requests. Refer to 4.1.1 Exceptions for more detail. Chapter

6 of the

SIM Reference Manual

has an in-depth explanation of how to use external interrupts.

2.10.1 Interrupt Priority Levels

An interrupt can be recognized on one of seven priority levels. These levels correspond to the numeric val-

ues of the external interrupt request lines. Level one (IRQ1) has the lowest priority; level seven (IRQ7) has

the highest priority level. Levels one through six can be masked by the interrupt priority level (IPL) field con-

tained in bits 10 through 8 of the CPU status register (SR). The level specified in the in the IPL field and all

levels below it are masked and are not recognized by the CPU. Level 7 is the only exception to this rule; it

cannot be masked. Out of reset, the IPL field is set to level 7. Thus, levels 1 through 6 will not be recognized

unless the IPL field is re-written to a lower value. The priority mask value can be changed by writing a new

value into the appropriate bits of the SR.

EXAMPLE:

To allow interrupts on levels 6 and 7 only, mask out levels 5 and below.

ANDI.W #$F8FF, SR

ORI.W #$0500, SR

2.10.2 Interrupt Arbitration Field

A number of modules in the MCU can request interrupt service. The CPU treats external interrupts as inter-

rupt service requests from the system integration module. The interrupt arbitration (IARB) field in the con-

figuration register of each module determines which module's interrupt requests take precedence when the

CPU receives more than one request at the same priority level. In order for interrupt requests to be acknowl-

edged, each module must be assigned a unique IARB number between $1 (lowest precedence) and $F

(highest precedence). Out of reset, the SIM IARB field has an initial value of $F, while other modules have

initial IARB values of $0.

332TUT EXT MEM CONN 3

MCU

ROM ENABLE

ADDR[16:1]

DATA

RAM

32K X 8

ROM

32K X 16

ADDR[13:1]

DATA[7:0]

DATA[15:0]

ADDR

DATA

ADDR

DATA

RAM

32K X 8

ADDR[13:1]

DATA[15:8]

ADDR

LOWER BYTE ENABLE

UPPER BYTE ENABLE

ADDR[16:0]

DATA[15:0]

CS0

CS1

CSBOOT

CS2

READ ENABLE (BOTH BYTES)

WE CEOE

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 55 56

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