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MC68332TUT/D MOTOROLA

2.10.3 Interrupt Vectors

Vectors are 32-bit addresses that point to the interrupt service routines (and other exception handlers). They

are stored in a data structure called the exception vector table. There are 256 vector addresses in the ex-

ception vector table; of these, 199 can be used for interrupts. The base address of the exception vector table

is determined by the value stored in the vector base register. A vector number is used to calculate the vector

address, or displacement into the exception vector table.

2.10.4 The Interrupt Acknowledge Cycle

After the CPU recognizes a valid interrupt request, it begins the interrupt acknowledge (IACK) cycle. The

CPU changes the IPL mask value to the level of the acknowledged interrupt to preclude lower-or-equal pri-

ority interrupt requests, then initiates a read cycle in CPU space. Since there is no dedicated IACK pin on

the MCU, an external IACK signal is usually provided by a chip-select pin. The CPU-space read serves two

purposes: it provides the address match required for chip-select assertion, and it acquires an interrupt vec-

tor number.

Vector numbers can be supplied by the device requesting interrupt service, or they can be generated auto-

matically. Vector numbers supplied by the device cause the CPU to access one of 192 user vectors in the

exception vector table; automatically generated vectors cause the CPU to access one of the seven autovec-

tors in the table. Each method of vector number acquisition requires a different form of IACK cycle termina-

tion. If a vector number is supplied, either the requesting device must terminate the IACK cycle with a

DSACK

signal or the chip-select logic must generate the DSACK signal internally. If an autovector is used,

an external device can assert the AVEC signal or an AVEC signal can be generated by the chip-select logic.

Since normal bus cycles occur in user or supervisor space, but an IACK cycle occurs in CPU space, the

same chip-select circuit cannot be used to terminate both an IACK cycle and a normal bus cycle.

2.10.4.1 User Vectors

Once an interrupting device has placed a user vector number on the external data bus in response to an

IACK signal from the MCU, either the device must terminate the IACK cycle with DSACK, or the chip-select

logic must generate DSACK internally. When the bus cycle has been terminated, the vector number is left-

shifted twice (multiplied by 4), then a 32-bit vector address is formed by concatenating the upper 22 bits of

the vector base register, the shifted value, and %00. The CPU then saves the current context, loads the 32-

bit vector into the PC, and begins to execute the service routine at that address.

An example is shown in Figure 16. Chip select 1 is configured for interrupt acknowledge and automatic gen-

eration of the DSACK signal. It is connected to the IACK pin of the peripheral. Because the processor drives

$FFFFFx onto the address bus and drives the function code pins to indicate CPU space during an IACK

cycle, the chip-select base address register must be programmed to $FFFX. When the CPU recognizes an

interrupt and initiates an IACK cycle, CS1 is asserted. In response, the peripheral drives an 8-bit vector

number onto the data bus. Chip-select logic then terminates the IACK cycle with DSACK.

Figure 16 Chip-Select Line Used For Interrupt Acknowledge

332TUT PERI CONN

D15

CS0

CS1

MC68332

PERIPHERAL

D6D14

D5D13

D4D12

D3D11

D2D10

D1D9

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