Motorola M68CPU32BUG Manuel d'utilisateur télécharger pdf (Page 33)

MC68332TUT/D MOTOROLA

org $0008 ;put the following code in memory after the reset vector.

DW $0000 ;The address of label INT is stored at location $0008,

DW INT ;which is the bus error vector

DW $0000 ;address error -- location $000C

DW INT

DW $0000 ;illegal instruction -- location $0010

DW INT

DW $0000 ;zero division -- location $0014

DW INT

DW $0000 CHK, CHK2 Instructions -- location $0018

DW INT

DW $0000 ;Last User Defined Interrupt -- stored at location $03FC

DW INT

In the actual program code, the following routine must be included:

INT {code to handle}

{the exception}

{goes here}

RTE ;return to the code that was previously being executed

4.1.4 CPU Status Register

The CPU status register contains some very important information.The SR is discussed on page 2-3 of the

CPU32 Reference Manual.

The fields are briefly described below:

Trace Enable [15:14] — If enabled, these bits cause the CPU to generate a trace exception after each

instruction executes, allowing a debugging program to monitor the execution of a program under test.

Out of reset, tracing is disabled. See page 6-13 in the

CPU32 Reference Manual

for more details.

Supervisor/User State [13] — The MCU has two privilege levels: supervisor and user. Not all registers

and instructions are available at the user level. Most programs operate at the user level and then pass

control to a supervisor routine by causing an exception. Out of reset, the supervisor/user state bit is set,

which means that the MCU is in supervisor mode. See pages 5-2 to 5-3 in the

CPU32 Reference Man-

ual

for more details.

Interrupt Priority Level[10:8] — The interrupt priority level determines which interrupts are recognized

and which are masked. Level 7 interrupts are always recognized. To allow other interrupts, this field

must contain a value that is lower than the interrupt priority level desired. For example, to allow level 6

interrupts, the value must be %101 or less. Out of reset, the field has a value of %111, which disables

all interrupts except for level 7 interrupts.

Condition Code Register [4:0] — The bits in the condition code register reflect the results of a previous

operation, and can be used for various condition tests, including conditional branches. There are ex-

tend, negative, zero, overflow, and carry bits.

4.2 Configuring the System Integration Module

Since the SIM determines important operating characteristics of the entire MCU, it should be the first module

after the CPU to be initialized. The following paragraphs discuss registers that it is important to initialize cor-

rectly.

4.2.1 System Integration Module Configuration Register (SIMCR)

The SIMCR controls module mapping for the MCU, internal use of the FREEZE signal, and the precedence

of simultaneous interrupt requests of the same priority. Configure the SIMCR as follows.

1. Set the state of the module mapping (MM) bit. Its reset state is a one, and it is one-time writable. MM

determines where the internal control registers are located in the system memory map. When MM =

0, register addresses range from $7FF000 to $7FFFFF; when MM =1, register addresses range from

$FFF000 to $FFFFFF.

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 55 56

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Motorola M68CPU32BUG Manuel d'utilisateur Page 33

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