Motorola M68CPU32BUG Manuel d'utilisateur télécharger pdf (Page 32)

OPERATING INSTRUCTIONS

M68332BCC/D 3-4 MOTOROLA

REV 1

3.2.2 Other MCU Resources Used by CPU32Bug

Avoid writing the value zero to bit 7 of the port F pin assignment register (PFPAR); such a value

disables the ABORT switch.

The software watchdog timer is disabled via a write-once register (SYPCR) during power-up or

reset, so the software watchdog timer cannot be used or re-enabled by the user unless the user

modifies the SYPCR_OR and SYPCR_AND parameters. Modification of the SYPCR_OR and

SYPCR_AND parameters is detailed in Appendix C of the M68CPU32BUG Debug Monitor

User’s Manual, M68CPU32BUG/AD1.

The monitor uses the system exception vectors, so they are unavailable to the BCC user. The

monitor debug exception vectors are listed in Table 3-4. The associated debugger facilities

(breakpoints, trace mode, etc.) will not operate if the vector offsets in the target program vector

table are changed.

Table 3-4. CPU32Bug Exception Vectors

Vector

Number Offset Exception CPU32Bug Commands

4 $10 Illegal Instruction breakpoints (Used by GO, GN, GT)

9 $24 Trace T, TC, TT

31 $7C Level 7 interrupt ABORT switch

47 $BC TRAP #15 System calls (see Chapter 5 of the M68CPU32BUG

Debug Monitor User’s Manual, M68CPU32BUG/AD1)

66 $108 User Defined Timer Trap #15 Calls ($4X)

Any change in the MC68332 MCU device clock speed causes a corresponding change in the SCI

baud rate. The operational speed of the MCU is determined by the clock and the synthesizer

control register value (SYNCR) or by an external clock signal applied to the EXTAL pin of the

MCU. The SCI baud rate is then set based on this system clock frequency. If changes are made to

the MCU system clock frequency, changes must be made to the customization parameter area

(FCRYSTAL or FEXTAL) so the correct baud rate can be calculated for SCI communications by

CPU32Bug. See the M68CPU32BUG Debug Monitor User’s Manual (M68CPU32BUG/AD1),

Appendix C for details.

Additionally, CPU32Bug writes a one (1) to the module mapping (MM) bit of the module

control register (MCR). This configures the register block to start at address $FFF000. As the

MM bit is a write-once bit, the user cannot clear it to move the register block to low memory

($7FF000). The user can move the register block by modifying the MCR_AND parameter

detailed in Appendix C of the M68CPU32BUG Debug Monitor User’s Manual,

M68CPU32BUG/AD1.

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 67 68

Pas de commentaire

Motorola M68CPU32BUG Manuel d'utilisateur Page 32