Motorola M68CPU32BUG Manuel d'utilisateur télécharger pdf (Page 54)

FUNCTIONAL DESCRIPTION

M68332BCC/D 4-4 MOTOROLA

REV 1

The serial communications interface (SCI) port provides a standard non-return to zero (NRZ)

mark/space format. Advanced error detection circuitry catches noise glitches to 1/16 of a bit time

in duration. Word length is software selectable between 8- or 9-bits, and the SCI modulus-type,

baud rate generator provides baud rates from 64 to 524k baud, based on a 16.77 MHz system

clock. The SCI features full- or half-duplex operation, with separate transmitter and receiver

enable bits and double buffering of data. Optional parity generation and detection provide either

even or odd parity check capability. Wake-up functions let the CPU run uninterrupted until either

a true idle line is detected or a new address byte is received.

4.2.1.4 Random Access Memory

2k bytes of static RAM are contained within the MC68332 MCU device. The RAM is used for

storage of variable and temporary data. RAM data size may be 8-bits (byte), 16-bits (word), or

32-bits (longword). The RAM can be mapped to any 2k byte boundary in the address map.

4.2.1.5 External Bus Interface

The external bus consists of 24 address lines and a 16-bit data bus. The data bus allows dynamic

sizing between 8- and 16-bit data accesses. A read-modify-write cycle (RMC) signal prevents

bus cycle interruption. External bus arbitration is accomplished by a three-line handshaking

interface.

4.2.1.6 Chip Selects

Twelve independently programmable chip selects provide fast, two-cycle external memory, or

peripheral access. Block size is programmable from 2 kilobytes through 1 megabyte. Accesses

can be selected for either 8- or 16-bit transfers. As many as 13 wait states can be programmed for

insertion during the access. All bus interface signals are automatically handled by the chip select

logic.

4.2.1.7 System Clock

An on-chip phase locked loop circuit generates the system clock signal to run the device up to

16.78 MHz from a 32.768 kHz watch crystal. The system speed can be changed dynamically,

providing either high performance or low power consumption under software control. The

system clock is a fully-static CMOS design, so it is possible to completely stop the system clock

via a low power stop instruction, while still retaining the contents of the registers and on-board

RAM.

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Motorola M68CPU32BUG Manuel d'utilisateur Page 54