Motorola M68CPU32BUG Manuel d'utilisateur Page 43
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-13
BV Block of Memory Verify BV
3.7 BLOCK OF MEMORY VERIFY
BV <range><del><data> [<del><increment>][;B|W|L]
where:
<data> and <increment> are both expression parameters
options:
B – Byte
W – Word
L – Longword
The BV command compares the specified range of memory against a data pattern. If an
increment is specified, then <data> is incremented by this value following each comparison,
otherwise <data> remains a constant value. Enter a negative increment to execute a decrementing
pattern. The data entered by the user is right-justified in either a byte, word, or longword field
length (as specified by the option selected). The default field length is W (word).
User-entered data or increment must fit into the data field or leading bits are truncated to size. If
truncation occurs, then a message is printed stating the actual data pattern and/or the actual
increment value.
If the range is specified using a count then the count is assumed to be in terms of the data size.
Truncation always occurs on byte or word sized fields when negative values are entered. For
example, entering "-1" internally becomes $FFFFFFFF which gets truncated to $FF for byte or
$FFFF for word sized fields. There is no difference internally between entering "-1" and entering
$FFFFFFFFF, so truncation occurs for byte or word sized fields.
If the upper address of the range is not on the correct boundary for an integer multiple of the data
to be verified, then data is verified to the last boundary before the upper address. Addresses
outside of the specified range are not read under any condition. ''Effective address'' messages
displayed by the command show the extent of the area read.
- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 3
- M68CPU32BUG/D REV 1 ii 4
- M68CPU32BUG/D REV 1 iii 5
- M68CPU32BUG/D REV 1 iv 6
- M68CPU32BUG/D REV 1 v 7
- LIST OF FIGURES 8
- LIST OF TABLES 8
- CHAPTER 1 9
- 1.1 INTRODUCTION 9
- 1.2 GENERAL DESCRIPTION 9
- GENERAL INFORMATION 10
- M68CPU32BUG/D REV 1 1-2 10
- 1.3 USING THIS MANUAL 11
- 1.5 SYSTEM RESTART 12
- 1.6 MEMORY REQUIREMENTS 13
- Figure 1-2. BCC Memory Map 14
- M68CPU32BUG/D REV 1 1-7 15
- M68CPU32BUG/D REV 1 1-8 16
- CHAPTER 2 17
- DEBUG MONITOR DESCRIPTION 17
- 2.1 INTRODUCTION 17
- M68CPU32BUG/D REV 1 2-2 18
- M68CPU32BUG/D REV 1 2-3 19
- M68CPU32BUG/D REV 1 2-4 20
- M68CPU32BUG/D REV 1 2-5 21
- M68CPU32BUG/D REV 1 2-6 22
- M68CPU32BUG/D REV 1 2-7 23
- M68CPU32BUG/D REV 1 2-8 24
- M68CPU32BUG/D REV 1 2-9 25
- M68CPU32BUG/D REV 1 2-10 26
- M68CPU32BUG/D REV 1 2-11 27
- 2.6 FUNCTION CODE SUPPORT 28
- M68CPU32BUG/D REV 1 2-13 29
- M68CPU32BUG/D REV 1 2-14 30
- CHAPTER 3 31
- 3.1 INTRODUCTION 31
- M68CPU32BUG/D REV 1 3-2 32
- BC Block of Memory Compare BC 33
- BF Block of Memory Fill BF 35
- BM Block of Memory Move BM 37
- BR Breakpoint Insert BR 39
- BS Block of Memory Search BS 40
- BV Block of Memory Verify BV 43
- DC Data Conversion DC 45
- DU Dump S-Records DU 46
- M68CPU32BUG/D REV 1 3-19 49
- M68CPU32BUG/D REV 1 3-20 50
- GN Go To Next Instruction GN 51
- GO Go Execute User Program GO 53
- M68CPU32BUG/D REV 1 3-26 56
- M68CPU32BUG/D REV 1 3-27 57
- HE Help HE 58
- M68CPU32BUG/D REV 1 3-31 61
- M68CPU32BUG/D REV 1 3-32 62
- M68CPU32BUG/D REV 1 3-33 63
- MA Macro Define/Display MA 64
- MAE Macro Edit MAE 67
- M68CPU32BUG/D REV 1 3-39 69
- MD Memory Display MD 70
- MM Memory Modify MM 72
- MS Memory Set MS 74
- M68CPU32BUG/D REV 1 3-45 75
- M68CPU32BUG/D REV 1 3-46 76
- M68CPU32BUG/D REV 1 3-47 77
- PA Printer Attached PA 78
- PF Port Format PF 79
- RD Register Display RD 82
- RESET Cold/Warm Reset RESET 86
- RM Register Modify RM 87
- RS Register Set RS 88
- SD Switch Directories SD 89
- T Trace T 90
- M68CPU32BUG/D REV 1 3-63 93
- Trace on change of flow: 94
- TM Transparent Mode TM 95
- M68CPU32BUG/D REV 1 3-66 96
- M68CPU32BUG/D REV 1 3-67 97
- M68CPU32BUG/D REV 1 3-68 98
- M68CPU32BUG/D REV 1 3-69 99
- DEBUG MONITOR COMMANDS 100
- M68CPU32BUG/D REV 1 3-70 100
- M68CPU32BUG/D REV 1 3-71 101
- M68CPU32BUG/D REV 1 3-72 102
- CHAPTER 4 103
- ASSEMBLER/DISASSEMBLER 103
- 4.1 INTRODUCTION 103
- 4.2SOURCE PROGRAM CODING 104
- M68CPU32BUG/D 4-3 105
- M68CPU32BUG/D 4-4 106
- Pseudo Registers 107
- Main Processor Registers 107
- M68CPU32BUG/D 4-6 108
- M68CPU32BUG/D 4-7 109
- M68CPU32BUG/D 4-8 110
- M68CPU32BUG/D 4-9 111
- M68CPU32BUG/D 4-10 112
- M68CPU32BUG/D 4-11 113
- 0000D000 6000BF68 BRA *-4096 114
- 0000D000 60FE BRA.B * 114
- 0000D000 4EF90000 D000 JMP * 114
- CHAPTER 5 115
- SYSTEM CALLS 115
- 5.1 INTRODUCTION 115
- 5.2 SYSTEM CALL ROUTINES 116
- M68CPU32BUG/D REV 1 5-3 117
- M68CPU32BUG/D REV 1 5-4 118
- M68CPU32BUG/D REV 1 5-5 119
- COUNT = 3 120
- COUNT = 3? 5<CR> 120
- COUNT = 5 120
- COUNT = 3? <CR> 120
- SYSCALL .CHKBRK 121
- BEQ BREAK 121
- M68CPU32BUG/D REV 1 5-8 122
- M68CPU32BUG/D REV 1 5-9 123
- .ERASLN Erase Line .ERASLN 124
- SYSCALL .INCHR Call .INCHR 125
- M68CPU32BUG/D REV 1 5-12 126
- M68CPU32BUG/D REV 1 5-13 127
- M68CPU32BUG/D REV 1 5-14 128
- MOVE.B D0,-(A7) 129
- Send character in D0 129
- SYSCALL .OUTCHR 129
- To default output port 129
- .OUTSTR .OUTSTR 130
- M68CPU32BUG/D REV 1 5-17 131
- PEA (A0) 132
- Long buffer address 132
- SYSCALL .READLN 132
- M68CPU32BUG/D REV 1 5-19 133
- SYSCALL .RETURN 134
- Return to CPU32Bug 134
- .SNDBRK Send Break .SNDBRK 135
- M68CPU32BUG/D REV 1 5-22 136
- SYSCALL .TM_INI 137
- Initialize timer 137
- .TM_RD Read Timer .TM_RD 138
- SYSCALL .TM_STR0 139
- Start Timer at T=0 .TM_STR0 140
- .WRITDLN .WRITDLN 141
- .WRITELN .WRITELN 143
- CHAPTER 6 145
- DIAGNOSTIC FIRMWARE GUIDE 145
- 6.1 INTRODUCTION 145
- 6.2 DIAGNOSTIC MONITOR 145
- M68CPU32BUG/D REV 1 6-2 146
- M68CPU32BUG/D REV 1 6-3 147
- 6.3 UTILITIES 148
- M68CPU32BUG/D REV 1 6-5 149
- CPU CPU Tests For The MCU CPU 150
- CPU A Register Test CPU A 151
- CPU B Instruction Test CPU B 152
- CPU C Address Mode Test CPU C 153
- M68CPU32BUG/D REV 1 6-10 154
- MT Memory Tests MT 155
- M68CPU32BUG/D REV 1 6-12 156
- MT A Set Function Code MT A 157
- MT B Set Start Address MT B 158
- MT C Set Stop Address MT C 159
- MT D Set Bus Data Width MT D 160
- MT E March Address Test MT E 161
- MT F Walk a Bit Test MT F 162
- MT G Refresh Test MT G 163
- MT H Random Byte Test MT H 164
- MT I Program Test MT I 165
- MT J Test and Set Test MT J 166
- BERR Bus Error Test BERR 167
- M68CPU32BUG/D REV 1 6-24 168
- APPENDIX A 169
- S-RECORD INFORMATION 169
- A.1 INTRODUCTION 169
- A.2 S-RECORD CONTENT 169
- A.3 S-RECORD TYPES 170
- A.4 S-RECORDS CREATION 171
- M68CPU32BUG REV 1 A-4 172
- APPENDIX B 173
- SELF-TEST ERROR MESSAGES 173
- B.1 INTRODUCTION 173
- M68CPU32BUG REV 1 B-2 174
- APPENDIX C 175
- USER CUSTOMIZATION 175
- C.1 INTRODUCTION 175
- C.2 CPU32BUG CUSTOMIZATION 176
- M68CPU32BUG REV 1 C-3 177
- C>DEL TMP.MX<CR> 178
- C>DEL C32B1.MX<CR> 178
- C.3 CUSTOMIZATION TABLE 179
- M68CPU32BUG REV 1 C-6 180
- M68CPU32BUG REV 1 C-7 181
- ROM AUTO BOOT VECTORS 182
- Periodic Interrupt Timer 183
- M68CPU32BUG REV 1 C-10 184
- M68CPU32BUG REV 1 C-11 185
- M68CPU32BUG REV 1 C-12 186
- M68CPU32BUG REV 1 C-13 187
- C.4 COMMUNICATION FORMATS 188
- M68CPU32BUG REV 1 C-15 189
- M68CPU32BUG REV 1 C-16 190
- Platform Board 191
- M68CPU32BUG REV 1 C-18 192
- Offset Value Comment 193
- M68CPU32BUG REV 1 C-20 194
- M68CPU32BUG REV 1 C-21 195
- M68CPU32BUG REV 1 C-22 196
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