Motorola M68CPU32BUG Manuel d'utilisateur Page 29
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-30
HE Help HE
NOMAL Disable Macro Expansion Listing
MD Memory Display
MM Memory Modify
M "Alias" for previous command
MS Memory Set
OF Offset Registers
PA Printer Attach
NOPA Printer Detach
PF Port Format
RD Register Display
RESET Warm/Cold Reset
RM Register Modify
RS Register Set
SD Switch Directory
T Trace Instruction
TC Trace on Change of Flow
TM Transparent Mode
TT Trace to Temporary Breakpoint
VE Verify S-Records
CPU32Bug>
To display the command TC, enter:
CPU32Bug>HE TC<CR>
TC Trace on Change of Flow
CPU32Bug>
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-27
GT Go To Temporary Breakpoint GT
CPU32Bug>GT 4006<CR>
Effective address: 00004006
Tempory breakpoint at $4006.
Effective address: 00004000 Current PC at $4000.
At Breakpoint
PC =00004006 SR =2711=TR:OFF_S_7_X...C VBR =00000000
SFC =0=F0 DFC =0=F0 USP =00003830 SSP* =00010000
D0 =00052A9C D1 =00000029 D2 =00000009 D3 =00000000
D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00010000
00004006 E289 LSR.L #1,D1
CPU32Bug>
Set another temporary breakpoint at $4002 and continue target program execution.
CPU32Bug>GT 4002<CR>
Effective address: 00004002
Tempory breakpoint at $4002.
Effective address: 00004006 Current PC at $4006.
At Breakpoint
PC =0000400E SR =2711=TR:OFF_S_7_X...C VBR =00000000
SFC =0=F0 DFC =0=F0 USP =00003830 SSP* =00010000
D0 =00052A9C D1 =00000000 D2 =000000FF D3 =00000000
04 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00010000
0000400E 60FE BRA.B $400E
Note that a breakpoint from the breakpoint table was encountered before the temproary
breakpoint.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 3
- 1.5 SYSTEM RESTART 5
- CHAPTER 1 5
- GENERAL INFORMATION 5
- 1.1 INTRODUCTION 5
- 1.2 GENERAL DESCRIPTION 5
- 1.3 USING THIS MANUAL 6
- 1.6 MEMORY REQUIREMENTS 7
- CHAPTER 2 9
- DEBUG MONITOR DESCRIPTION 9
- 2.1 INTRODUCTION 9
- Freescale Semiconductor, Inc 10
- 2.6 FUNCTION CODE SUPPORT 13
- CHAPTER 3 16
- DEBUG MONITOR COMMANDS 16
- 3.1 INTRODUCTION 16
- BC Block of Memory Compare BC 17
- BF Block of Memory Fill BF 17
- BS Block of Memory Search BS 19
- BM Block of Memory Move BM 19
- BR Breakpoint Insert BR 20
- BV Block of Memory Verify BV 21
- DU Dump S-Records DU 23
- DC Data Conversion DC 23
- GN Go To Next Instruction GN 25
- GO Go Execute User Program GO 27
- HE Help HE 29
- MA Macro Define/Display MA 31
- MAE Macro Edit MAE 33
- MM Memory Modify MM 35
- MD Memory Display MD 36
- MS Memory Set MS 38
- PF Port Format PF 39
- PA Printer Attached PA 40
- RD Register Display RD 41
- RS Register Set RS 43
- RESET Cold/Warm Reset RESET 44
- RM Register Modify RM 44
- T Trace T 45
- SD Switch Directories SD 45
- TM Transparent Mode TM 48
- 4.2SOURCE PROGRAM CODING 51
- CHAPTER 4 52
- ASSEMBLER/DISASSEMBLER 52
- 4.1 INTRODUCTION 52
- 5.2 SYSTEM CALL ROUTINES 57
- CHAPTER 5 58
- SYSTEM CALLS 58
- 5.1 INTRODUCTION 58
- .ERASLN Erase Line .ERASLN 61
- .OUTSTR .OUTSTR 66
- .SNDBRK Send Break .SNDBRK 68
- .TM_RD Read Timer .TM_RD 70
- .WRITELN .WRITELN 71
- .WRITDLN .WRITDLN 71
- 6.3 UTILITIES 73
- CHAPTER 6 73
- DIAGNOSTIC FIRMWARE GUIDE 73
- 6.1 INTRODUCTION 73
- 6.2 DIAGNOSTIC MONITOR 73
- CPU B Instruction Test CPU B 75
- CPU CPU Tests For The MCU CPU 76
- CPU A Register Test CPU A 76
- CPU C Address Mode Test CPU C 77
- MT Memory Tests MT 78
- MT D Set Bus Data Width MT D 79
- MT A Set Function Code MT A 79
- MT B Set Start Address MT B 80
- MT C Set Stop Address MT C 80
- MT H Random Byte Test MT H 81
- MT E March Address Test MT E 81
- MT F Walk a Bit Test MT F 82
- MT G Refresh Test MT G 82
- MT I Program Test MT I 83
- MT J Test and Set Test MT J 84
- BERR Bus Error Test BERR 84
- APPENDIX A 85
- S-RECORD INFORMATION 85
- A.1 INTRODUCTION 85
- A.2 S-RECORD CONTENT 85
- A.3 S-RECORD TYPES 86
- A.4 S-RECORDS CREATION 86
- C.2 CPU32BUG CUSTOMIZATION 87
- APPENDIX B 87
- SELF-TEST ERROR MESSAGES 87
- B.1 INTRODUCTION 87
- APPENDIX C 88
- USER CUSTOMIZATION 88
- C.1 INTRODUCTION 88
- C.3 CUSTOMIZATION TABLE 90
- C.4 COMMUNICATION FORMATS 93
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