Motorola M68CPU32BUG Manuel d'utilisateur Page 43
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DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-58
RS Register Set RS
3.28 REGISTER SET
RS <reg>[<exp>][;A]
Use the RS command to display or change a single target register. The default offset register
value is always added to <exp> unless overridden by specifically including an offset register. See
the OF (offset register) command.
The ;A option is only valid when <reg> is an offset register, i.e. R0 - R7. Use the ;A option to set
<reg> as the automatic register. If R7 is specified, no <exp> is allowed (R7 cannot be changed).
See the OF (offset register) command.
EXAMPLES
CPU32Bug>RS PC 40*1000+4<CR>
PC =00040004
CPU32Bug>
CPU32Bug>OF R4;A<CR>
R4*00000000 00000000? 4000 4FFF<CR> Set up automatic offset register R4.
CPU32Bug>RS PC 124<CR>
PC =00004124 Set PC=$124+R4.
CPU32Bug>RS A4 32A<CR>
A4 =0000432A Set A4=$32A+R4.
CPU32Bug>RS A5 400+R7<CR>
A5 =00000400 Set A5 equal to absolute location $400
($400+R7).
CPU32Bug>
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-55
RD Register Display RD
The source and destination function code registers (SFC, DFC) include a two character
mnemonic:
Function Code Mnemonic Description
0 F0 Undefined
1 UD User Data
2 UP User Program
3 F3 Undefined
4 F4 Undefined
5 SD Supervisor Data
6 SP Supervisor Program
7 CS CPU Space
To set the display to D6 and A3 only.
CPU32Bug>RD =D6/A3<CR>
D6 =00000000 A3 =00000000
00003000 4AFC ILLEGAL
CPU32Bug>
Note that the above sequence sets the display to D6 only and then adds register A3 to the display.
To restore all the MPU registers.
CPU32Bug>rd +mpu<CR>
PC =00003000 SR =2700=TR:OFF_S_7_..... VBR =00000000
SFC =0=F0 DFC =0=F0 USP =00003830 SSP* =00004000
D0 =00000000 D1 =00000000 D2 =00000000 D3 =00000000
D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00004000
00003000 4AFC ILLEGAL
CPU32Bug>
Note that an equivalent command is ’’RD +PC-A7’’ or ’’RD =PC-A7’’.
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 3
- 1.5 SYSTEM RESTART 5
- CHAPTER 1 5
- GENERAL INFORMATION 5
- 1.1 INTRODUCTION 5
- 1.2 GENERAL DESCRIPTION 5
- 1.3 USING THIS MANUAL 6
- 1.6 MEMORY REQUIREMENTS 7
- CHAPTER 2 9
- DEBUG MONITOR DESCRIPTION 9
- 2.1 INTRODUCTION 9
- Freescale Semiconductor, Inc 10
- 2.6 FUNCTION CODE SUPPORT 13
- CHAPTER 3 16
- DEBUG MONITOR COMMANDS 16
- 3.1 INTRODUCTION 16
- BC Block of Memory Compare BC 17
- BF Block of Memory Fill BF 17
- BS Block of Memory Search BS 19
- BM Block of Memory Move BM 19
- BR Breakpoint Insert BR 20
- BV Block of Memory Verify BV 21
- DU Dump S-Records DU 23
- DC Data Conversion DC 23
- GN Go To Next Instruction GN 25
- GO Go Execute User Program GO 27
- HE Help HE 29
- MA Macro Define/Display MA 31
- MAE Macro Edit MAE 33
- MM Memory Modify MM 35
- MD Memory Display MD 36
- MS Memory Set MS 38
- PF Port Format PF 39
- PA Printer Attached PA 40
- RD Register Display RD 41
- RS Register Set RS 43
- RESET Cold/Warm Reset RESET 44
- RM Register Modify RM 44
- T Trace T 45
- SD Switch Directories SD 45
- TM Transparent Mode TM 48
- 4.2SOURCE PROGRAM CODING 51
- CHAPTER 4 52
- ASSEMBLER/DISASSEMBLER 52
- 4.1 INTRODUCTION 52
- 5.2 SYSTEM CALL ROUTINES 57
- CHAPTER 5 58
- SYSTEM CALLS 58
- 5.1 INTRODUCTION 58
- .ERASLN Erase Line .ERASLN 61
- .OUTSTR .OUTSTR 66
- .SNDBRK Send Break .SNDBRK 68
- .TM_RD Read Timer .TM_RD 70
- .WRITELN .WRITELN 71
- .WRITDLN .WRITDLN 71
- 6.3 UTILITIES 73
- CHAPTER 6 73
- DIAGNOSTIC FIRMWARE GUIDE 73
- 6.1 INTRODUCTION 73
- 6.2 DIAGNOSTIC MONITOR 73
- CPU B Instruction Test CPU B 75
- CPU CPU Tests For The MCU CPU 76
- CPU A Register Test CPU A 76
- CPU C Address Mode Test CPU C 77
- MT Memory Tests MT 78
- MT D Set Bus Data Width MT D 79
- MT A Set Function Code MT A 79
- MT B Set Start Address MT B 80
- MT C Set Stop Address MT C 80
- MT H Random Byte Test MT H 81
- MT E March Address Test MT E 81
- MT F Walk a Bit Test MT F 82
- MT G Refresh Test MT G 82
- MT I Program Test MT I 83
- MT J Test and Set Test MT J 84
- BERR Bus Error Test BERR 84
- APPENDIX A 85
- S-RECORD INFORMATION 85
- A.1 INTRODUCTION 85
- A.2 S-RECORD CONTENT 85
- A.3 S-RECORD TYPES 86
- A.4 S-RECORDS CREATION 86
- C.2 CPU32BUG CUSTOMIZATION 87
- APPENDIX B 87
- SELF-TEST ERROR MESSAGES 87
- B.1 INTRODUCTION 87
- APPENDIX C 88
- USER CUSTOMIZATION 88
- C.1 INTRODUCTION 88
- C.3 CUSTOMIZATION TABLE 90
- C.4 COMMUNICATION FORMATS 93
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