Motorola M68CPU32BUG Manuel d'utilisateur Page 7

  • Télécharger
  • Ajouter à mon manuel
  • Imprimer
  • Page
    / 98
  • Table des matières
  • MARQUE LIVRES
  • Noté. / 5. Basé sur avis des utilisateurs
Vue de la page 6
GENERAL INFORMATION
M68CPU32BUG/D REV 1 1-8
GENERAL INFORMATION
M68CPU32BUG/D REV 1 1-5
1.5.3 Break
The BREAK key on the terminal keyboard initiates a break. Break does not generate an
interrupt. The only time break is recognized is when characters are sent or received by the
debugger console. Break removes any breakpoints in the user code and keeps the breakpoint table
intact. Break does not, however, take a snapshot of the machine state nor does it display the
target registers. It is useful for terminating active debugger commands that are outputing large
blocks of data.
NOTE
When using terminal emulation programs such as ProComm or
Kermit, the BREAK key on the keyboard is local to the emulation
program and may not be transmitted to the BCC. Consult your
emulation program’s user manual for the procedure on sending a
BREAK signal to the port connected to the BCC.
1.6 MEMORY REQUIREMENTS
The program portion of CPU32Bug is approximately 64k bytes of code. The EPROM on-board
the BCC contains 128k bytes and is mapped at locations $E0000 to $FFFFF. However, the
CPU32Bug code is position-independent and can execute anywhere in memory. The second half
of the EPROM ($F0000 - $FFFFF) is blank and available for user programs. See Appendix C
CPU32Bug Customization.
CPU32Bug requires a minimum of 12k bytes of random access memory (RAM) to operate. This
memory may be either off-board system memory (i.e., on an external memory board) or BCC on-
board RAM. On-board RAM allows stand-alone operation of the BCC.
The first 12k bytes are used for CPU32Bug stack and static variable space and the rest of
memory is reserved as user space. Whenever the BCC is reset, the target program counter is
initialized to the beginning user space address and the target stack pointers are initialized to
addresses at the end of the user space. The target instruction stack pointer (SSP) is set to the top
of the user space. Register initialization is done solely as a convenience for the user. Consult the
CPU32 Reference Manual for information regarding actual register values during a power-
on/reset.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Vue de la page 6
1 2 3 4 5 6 7 8 9 10 11 12 ... 97 98

Commentaires sur ces manuels

Pas de commentaire