Motorola M68CPU32BUG Manuel d'utilisateur Page 78
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
DIAGNOSTIC FIRMWARE GUIDE
M68CPU32BUG/D REV 1 6-10
CPU D Exception Processing Test CPU D
6.4.4 Exception Processing Test
CPU32Diag>CPU D
CPU D tests many of the exception processing routines of the MCU, but not the interrupt auto
vectors or any of the floating point co-processor vectors.
EXAMPLE
After the command has been issued, the following line is printed:
D CPU Exception Processing Test......Running ---------->
If any part of the test fails, then the display appears as follows.
D CPU Exception Processing Test......Running ---------->..... FAILED
Test Failed Vector # XXX
# XXX is the hexadecimal exception vector offset, as explained in the CPU32 Reference
Manual.
However, if the failure involves taking an exception different from that being tested, the
display is:
D CPU Exception Processing Test......Running ---------->..... FAILED
Unexpected exception taken to Vector # XXX
If all parts of the test are completed correctly, then the test passes.
D CPU Exception Processing Test......Running ----------> PASSED
DIAGNOSTIC FIRMWARE GUIDE
M68CPU32BUG/D REV 1 6-11
MT Memory Tests MT
6.5 MEMORY TESTS (MT)
The memory tests are a series of diagnostics which verify random access memory (read/write)
that may or may not reside on the M68300EVS evaluation system. Default is the BCC on-board
RAM. To test off-board RAM, change Start and Stop Addresses per MT B and MT C as
described in the following paragraphs. Memory tests are listed in Table 6-2.
NOTE
If one or more memory tests are attempted at an address where there is no
memory, a bus error message appears, giving the details of the problem.
Table 6-2. Memory Diagnostic Tests
MONITOR COMMAND TITLE
MT A Set Function Code
MT B Set Start Address
MT C Set Stop Address
MT D Set Bus Data Width
MT E March Address Test
MT F Walk a Bit Test
MT G Refresh Test
MT H Random Byte Test
MT I Program Test
MT J TAS Test
The following hardware is required to perform these tests.
• M68300EVK - Module being tested
• Video display terminal or host computer
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- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 3
- 1.5 SYSTEM RESTART 5
- CHAPTER 1 5
- GENERAL INFORMATION 5
- 1.1 INTRODUCTION 5
- 1.2 GENERAL DESCRIPTION 5
- 1.3 USING THIS MANUAL 6
- 1.6 MEMORY REQUIREMENTS 7
- CHAPTER 2 9
- DEBUG MONITOR DESCRIPTION 9
- 2.1 INTRODUCTION 9
- Freescale Semiconductor, Inc 10
- 2.6 FUNCTION CODE SUPPORT 13
- CHAPTER 3 16
- DEBUG MONITOR COMMANDS 16
- 3.1 INTRODUCTION 16
- BC Block of Memory Compare BC 17
- BF Block of Memory Fill BF 17
- BS Block of Memory Search BS 19
- BM Block of Memory Move BM 19
- BR Breakpoint Insert BR 20
- BV Block of Memory Verify BV 21
- DU Dump S-Records DU 23
- DC Data Conversion DC 23
- GN Go To Next Instruction GN 25
- GO Go Execute User Program GO 27
- HE Help HE 29
- MA Macro Define/Display MA 31
- MAE Macro Edit MAE 33
- MM Memory Modify MM 35
- MD Memory Display MD 36
- MS Memory Set MS 38
- PF Port Format PF 39
- PA Printer Attached PA 40
- RD Register Display RD 41
- RS Register Set RS 43
- RESET Cold/Warm Reset RESET 44
- RM Register Modify RM 44
- T Trace T 45
- SD Switch Directories SD 45
- TM Transparent Mode TM 48
- 4.2SOURCE PROGRAM CODING 51
- CHAPTER 4 52
- ASSEMBLER/DISASSEMBLER 52
- 4.1 INTRODUCTION 52
- 5.2 SYSTEM CALL ROUTINES 57
- CHAPTER 5 58
- SYSTEM CALLS 58
- 5.1 INTRODUCTION 58
- .ERASLN Erase Line .ERASLN 61
- .OUTSTR .OUTSTR 66
- .SNDBRK Send Break .SNDBRK 68
- .TM_RD Read Timer .TM_RD 70
- .WRITELN .WRITELN 71
- .WRITDLN .WRITDLN 71
- 6.3 UTILITIES 73
- CHAPTER 6 73
- DIAGNOSTIC FIRMWARE GUIDE 73
- 6.1 INTRODUCTION 73
- 6.2 DIAGNOSTIC MONITOR 73
- CPU B Instruction Test CPU B 75
- CPU CPU Tests For The MCU CPU 76
- CPU A Register Test CPU A 76
- CPU C Address Mode Test CPU C 77
- MT Memory Tests MT 78
- MT D Set Bus Data Width MT D 79
- MT A Set Function Code MT A 79
- MT B Set Start Address MT B 80
- MT C Set Stop Address MT C 80
- MT H Random Byte Test MT H 81
- MT E March Address Test MT E 81
- MT F Walk a Bit Test MT F 82
- MT G Refresh Test MT G 82
- MT I Program Test MT I 83
- MT J Test and Set Test MT J 84
- BERR Bus Error Test BERR 84
- APPENDIX A 85
- S-RECORD INFORMATION 85
- A.1 INTRODUCTION 85
- A.2 S-RECORD CONTENT 85
- A.3 S-RECORD TYPES 86
- A.4 S-RECORDS CREATION 86
- C.2 CPU32BUG CUSTOMIZATION 87
- APPENDIX B 87
- SELF-TEST ERROR MESSAGES 87
- B.1 INTRODUCTION 87
- APPENDIX C 88
- USER CUSTOMIZATION 88
- C.1 INTRODUCTION 88
- C.3 CUSTOMIZATION TABLE 90
- C.4 COMMUNICATION FORMATS 93
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