Motorola M68CPU32BUG Manuel d'utilisateur Page 81
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Noté. / 5. Basé sur avis des utilisateurs
DIAGNOSTIC FIRMWARE GUIDE
M68CPU32BUG/D REV 1 6-20
MT H Random Byte Test MT H
6.5.8 Random Byte Test
CPU32Diag>MT H
MT H performs a random byte test from Start Address to Stop Address. The random byte test
has been implemented in this manner:
1. A register is loaded with the value $ECA86420.
2. For each memory location:
• Copy the contents of the register to the memory location, one byte at a time.
• Add $02468ACE to the contents of the register.
• Proceed to next memory location.
3. Reload $ECA86420 into the register.
4. For each memory location:
• Compare the contents of the memory to the register to verify that the
contents are good, one byte at a time.
• Add $02468ACE to the contents of the register.
• Proceed to next memory location.
EXAMPLE
After the command is entered, the display should appear as follows:
H MT Random Byte Test................Running ---------->
If an error occurs, then the memory location and other related information are displayed.
H MT Random Byte Test................Running ---------->..... FAILED
(error-related information)
If no errors occur, then the display appears as follows:
H MT Random Byte Test................Running ----------> PASSED
DIAGNOSTIC FIRMWARE GUIDE
M68CPU32BUG/D REV 1 6-17
MT E March Address Test MT E
6.5.5 March Address Test
CPU32Diag>MT E
MT E performs a march address test from Start Address to Stop Address. The march address test
has been implemented in this manner:
1. All memory locations from Start Address up to Stop Address are cleared to 0.
2. Beginning at Stop Address and proceeding downward to Start Address, each memory
location is checked for bits that did not clear and then the contents are changed to all
F’s (all the bits are set). This process reveals address lines that are stuck high.
3. Beginning at Start Address and proceeding upward to Stop Address, each memory
location is checked for bits that did not set and then the memory location is again
cleared to 0. This process reveals address lines that are stuck low.
EXAMPLE
After the command is entered, the display should appear as follows:
E MT March Addr. Test................Running ---------->
If an error is encountered, then the memory location and other related information are
displayed.
E MT March Addr. Test................Running ---------->..... FAILED
(error-related information)
If no errors are encountered, then the display appears as follows:
E MT March Addr. Test................Running ----------> PASSED
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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- M68CPU32BUG DEBUG MONITOR 1
- USER’S MANUAL 1
- M68CPU32BUG/D 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 3
- 1.5 SYSTEM RESTART 5
- CHAPTER 1 5
- GENERAL INFORMATION 5
- 1.1 INTRODUCTION 5
- 1.2 GENERAL DESCRIPTION 5
- 1.3 USING THIS MANUAL 6
- 1.6 MEMORY REQUIREMENTS 7
- CHAPTER 2 9
- DEBUG MONITOR DESCRIPTION 9
- 2.1 INTRODUCTION 9
- Freescale Semiconductor, Inc 10
- 2.6 FUNCTION CODE SUPPORT 13
- CHAPTER 3 16
- DEBUG MONITOR COMMANDS 16
- 3.1 INTRODUCTION 16
- BC Block of Memory Compare BC 17
- BF Block of Memory Fill BF 17
- BS Block of Memory Search BS 19
- BM Block of Memory Move BM 19
- BR Breakpoint Insert BR 20
- BV Block of Memory Verify BV 21
- DU Dump S-Records DU 23
- DC Data Conversion DC 23
- GN Go To Next Instruction GN 25
- GO Go Execute User Program GO 27
- HE Help HE 29
- MA Macro Define/Display MA 31
- MAE Macro Edit MAE 33
- MM Memory Modify MM 35
- MD Memory Display MD 36
- MS Memory Set MS 38
- PF Port Format PF 39
- PA Printer Attached PA 40
- RD Register Display RD 41
- RS Register Set RS 43
- RESET Cold/Warm Reset RESET 44
- RM Register Modify RM 44
- T Trace T 45
- SD Switch Directories SD 45
- TM Transparent Mode TM 48
- 4.2SOURCE PROGRAM CODING 51
- CHAPTER 4 52
- ASSEMBLER/DISASSEMBLER 52
- 4.1 INTRODUCTION 52
- 5.2 SYSTEM CALL ROUTINES 57
- CHAPTER 5 58
- SYSTEM CALLS 58
- 5.1 INTRODUCTION 58
- .ERASLN Erase Line .ERASLN 61
- .OUTSTR .OUTSTR 66
- .SNDBRK Send Break .SNDBRK 68
- .TM_RD Read Timer .TM_RD 70
- .WRITELN .WRITELN 71
- .WRITDLN .WRITDLN 71
- 6.3 UTILITIES 73
- CHAPTER 6 73
- DIAGNOSTIC FIRMWARE GUIDE 73
- 6.1 INTRODUCTION 73
- 6.2 DIAGNOSTIC MONITOR 73
- CPU B Instruction Test CPU B 75
- CPU CPU Tests For The MCU CPU 76
- CPU A Register Test CPU A 76
- CPU C Address Mode Test CPU C 77
- MT Memory Tests MT 78
- MT D Set Bus Data Width MT D 79
- MT A Set Function Code MT A 79
- MT B Set Start Address MT B 80
- MT C Set Stop Address MT C 80
- MT H Random Byte Test MT H 81
- MT E March Address Test MT E 81
- MT F Walk a Bit Test MT F 82
- MT G Refresh Test MT G 82
- MT I Program Test MT I 83
- MT J Test and Set Test MT J 84
- BERR Bus Error Test BERR 84
- APPENDIX A 85
- S-RECORD INFORMATION 85
- A.1 INTRODUCTION 85
- A.2 S-RECORD CONTENT 85
- A.3 S-RECORD TYPES 86
- A.4 S-RECORDS CREATION 86
- C.2 CPU32BUG CUSTOMIZATION 87
- APPENDIX B 87
- SELF-TEST ERROR MESSAGES 87
- B.1 INTRODUCTION 87
- APPENDIX C 88
- USER CUSTOMIZATION 88
- C.1 INTRODUCTION 88
- C.3 CUSTOMIZATION TABLE 90
- C.4 COMMUNICATION FORMATS 93
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