Motorola MVME712A/D3 Manuel d'utilisateur

MVME147SMPU VMEmodule User’sManualMVME147S/D3April 2000 Edition

xiLocal Bus Multiport Arbiter ...5-21Reset...

5-16 Computer Group Literature Center Web SiteFunctional Description5Figure 5-2. Timings Guaranteed by MVME147S #ti2992022729 0003WRI T EVAL I DA0-A1

Functional Descriptionhttp://www.motorola.com/computer/literature 5-175EEPROM Power Up/Power Down ConsiderationsThe MVME147S provides no protection ag

5-18 Computer Group Literature Center Web SiteFunctional Description5PCC PCC %XXXX0011 ProgLANCE PCC PCC %XXXX0100 ProgSCSI Port PCC PCC %XXXX0101 Pro

Functional Descriptionhttp://www.motorola.com/computer/literature 5-195Front Panel Switches and IndicatorsThere are two switches on the front panel of

5-20 Computer Group Literature Center Web SiteFunctional Description5In mode 3, parity checking is performed for all bus masters and parity errors are

Functional Descriptionhttp://www.motorola.com/computer/literature 5-215LANCE DRAM AccessesWhen the LANCE needs to access DRAM it requests local bus ma

5-22 Computer Group Literature Center Web SiteFunctional Description5ResetThere are five sources of reset on the MVME147S. Sources of Bus Error (BERR*

Functional Descriptionhttp://www.motorola.com/computer/literature 5-235VMEbus BERR*The VMEbus BERR* occurs when the BERR* signal line is activated on

5-24 Computer Group Literature Center Web SiteFunctional Description51. An interrupt can happen during the execution of the bus error handler (before

Functional Descriptionhttp://www.motorola.com/computer/literature 5-255WAITRMC bit can be a performance penalty. When the bit is set, the MVME147S wai

1-111General InformationIntroductionThis manual provides general information, preparation for use and installation, operating instructions, and functi

5-26 Computer Group Literature Center Web SiteFunctional Description5Figure 5-3. MVME147S Block DiagramFPC AND DATABUS PULLUPSSHEET 9RAM ARRAYSHEETS

IN-1IndexAABORT 3-1Abort Interrupt Control Register 4-12ABORT switch 3-2, 5-11, 5-19ABORT Switch (S1) 3-2AC Fail Interrupt Control Register 4-7AC Fail

IndexIN-2 Computer Group Literature Center Web SiteINDEXEEEPROM Power Up/Power Down Consider-ations 5-17Encoding of the Interrupt ID 4-35erasing writi

http://www.motorola.com/computer/literature IN-3INDEXMManual Terminology 1-8MARMC 5-24Master Address Modifier Register 4-32Master Configuration Regist

IndexIN-4 Computer Group Literature Center Web SiteINDEXSCSI Reset 5-9SCSI terminator power 2-12Serial Communications Controller 5-11Serial Interface

http://www.motorola.com/computer/literature IN-5INDEXVMEbus Requester 5-5VMEbus Requester Configuration Register4-24VMEbus Short I/O Memory Map 3-11VM

1-2 Computer Group Literature Center Web SiteGeneral Information1FeaturesThe features of the MVME147S include: ❏ MC68030 microprocessor ❏ Floating-Poi

Specificationshttp://www.motorola.com/computer/literature 1-31SpecificationsThe MVME147S specifications are given in the following table. Table 1-2.

1-4 Computer Group Literature Center Web SiteGeneral Information1Cooling RequirementsMotorola VMEmodules are specified, designed, and tested to operat

Specificationshttp://www.motorola.com/computer/literature 1-51axial fans, rated at 100 CFM per fan, is placed directly under the MVME card cage. The i

1-6 Computer Group Literature Center Web SiteGeneral Information1General DescriptionThe MVME147S is a double-high VMEmodule and is best utilized in a

Related Specificationshttp://www.motorola.com/computer/literature 1-71To obtain the most up-to-date product information in PDF or HTML format, visit h

1-8 Computer Group Literature Center Web SiteGeneral Information1Local Area Network Controller Am7990 (LANCE), Technical Manual, order number 06363A,

2-122Hardware Preparation andInstallationIntroductionThis chapter provides the unpacking, hardware preparation, and installation instructions for the

NoticeWhile reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omission

2-2 Computer Group Literature Center Web SiteHardware Preparation and Installation2❏ ROM configuration select (J1, J2) ❏ System controller select (J3)

Unpacking Instructionshttp://www.motorola.com/computer/literature 2-32Figure 2-1. MVME147S Header Locations P1A1B1C1A32B32C32P2A32B32C32A1B1C1DS1J8J7

2-4 Computer Group Literature Center Web SiteHardware Preparation and Installation2ROM Configuration Select Headers (J1, J2)The MVME147S supports vari

Unpacking Instructionshttp://www.motorola.com/computer/literature 2-52128K x 8 ROM/PROM/EPROMJ2 - BANK 1 J1 - BANK 22 4 6 8 10 12 14 16 18135791113151

2-6 Computer Group Literature Center Web SiteHardware Preparation and Installation2The following figures show the definitions of the ROM/PROM/EPROM/EE

Unpacking Instructionshttp://www.motorola.com/computer/literature 2-72The sockets are installed on the module with pins oriented as shown below: 7 512

2-8 Computer Group Literature Center Web SiteHardware Preparation and Installation2CONFIGURATION CONFIGURATION5678 8765+5V +5V +5V A20 1 32 +5V +5V +5

Unpacking Instructionshttp://www.motorola.com/computer/literature 2-92System Controller Select Header (J3)Header J3 allows the user to select the MVME

2-10 Computer Group Literature Center Web SiteHardware Preparation and Installation2Serial Port 4 Clock Configuration Select Headers (J8, J9)Serial po

Installation Instructionshttp://www.motorola.com/computer/literature 2-1123. Remove the filler panel(s) from the appropriate card slot(s) at the front

PrefaceThis manual provides general information, hardware preparation, installation instructions, operating instructions, programming, and functional

2-12 Computer Group Literature Center Web SiteHardware Preparation and Installation25. Remove IACK and BG jumpers from header on chassis backplane for

3-133Operating InstructionsIntroductionThis chapter provides the necessary information to use the MVME147S module in a system configuration. Controls

3-2 Computer Group Literature Center Web SiteOperating Instructions3ABORT Switch S1A software ABORT switch S1 is located on the front panel. The ABORT

Controls and Indicatorshttp://www.motorola.com/computer/literature 3-33Table 3-1. Front Panel LEDs and MVME147S StatusFAILSTATUS RUNMVME147S StatusDS

3-4 Computer Group Literature Center Web SiteOperating Instructions3Memory MapsThere are two points of view or memory maps on the MVME147S: the mappin

Memory Mapshttp://www.motorola.com/computer/literature 3-53Program and Data Address SpacesThe memory map of devices that respond in user data, user pr

3-6 Computer Group Literature Center Web SiteOperating Instructions3The local I/O devices portion of the MC68030 main memory map is shown in the follo

Memory Mapshttp://www.motorola.com/computer/literature 3-73CPU Address SpaceThe MVME147S responds to two types of CPU space cycles: coprocessor and in

3-8 Computer Group Literature Center Web SiteOperating Instructions3Coprocessor Register MapThe MC68882 is the only coprocessor on the MVME147S. The m

Memory Mapshttp://www.motorola.com/computer/literature 3-93VMEbus Memory MapThe following paragraphs describe the mapping of MVME147S resources as vie

Safety SummaryThe following general safety precautions must be observed during all phases of operation, service, and repair of thisequipment. Failure

3-10 Computer Group Literature Center Web SiteOperating Instructions30111115 x DRAMsize(16 x DRAMsize)-1 1,21000016 x DRAMsize(17 x DRAMsize)-1 1,2100

Memory Mapshttp://www.motorola.com/computer/literature 3-113VMEbus Short I/O Memory MapThe VMEchip Global Control and Status Register (GCSR) Set appea

3-12 Computer Group Literature Center Web SiteOperating Instructions3VMEbus Interrupt Acknowledge MapThe VMEbus distinguishes interrupt acknowledge cy

4-144ProgrammingIntroductionThis chapter provides the information needed to program the Peripheral Channel Controller (PCC) and the VMEchip. Programmi

4-2 Computer Group Literature Center Web SiteProgramming432-Bit Registers16-Bit Registers8-Bit RegistersTable 4-1. PCC Overall ViewAddress Register F

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-34Byte Count RegisterThis 32-bit read/write register contai

4-4 Computer Group Literature Center Web SiteProgramming4Timer 1 Preload RegisterThis 16-bit read/write register holds the tick timer preload value. W

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-54Timer 1 Interrupt Control RegisterThe table below shows t

4-6 Computer Group Literature Center Web SiteProgramming4Timer 2 Interrupt Control RegisterThe table below shows the timer 2 interrupt control registe

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-74Timer 2 Control RegisterThe table below shows the timer 2

All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized manufacturers, with a flammability rating of 94V-0. !WARNINGThis equipment

4-8 Computer Group Literature Center Web SiteProgramming4Watchdog Timer Control RegisterThe table below shows the watchdog timer control register. Not

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-94Note Bit set and clear instructions should not be used o

4-10 Computer Group Literature Center Web SiteProgramming4DMA Interrupt Control RegisterThe table below shows the DMA interrupt control register. Note

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-114DMA Control and Status RegisterThe table below shows the

4-12 Computer Group Literature Center Web SiteProgramming4DMA Status RegisterThe table below shows the DMA status register. Abort Interrupt Control Re

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-134Note Bit set and clear instructions should not be used

4-14 Computer Group Literature Center Web SiteProgramming4All bits are cleared by reset. General Purpose Control RegisterThe table below shows the gen

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-154LAN Interrupt Control RegisterThe table below shows the

4-16 Computer Group Literature Center Web SiteProgramming4General Purpose Status RegisterThe table below shows the general purpose status register. SC

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-174Slave Base Address RegisterThe table below shows the sla

viiContentsCHAPTER 1 General InformationIntroduction...

4-18 Computer Group Literature Center Web SiteProgramming40 1 0 0 1 9 x DRAMsize (10 x DRAMsize)-1 1,20 1 0 1 0 10 x DRAMsize (11 x DRAMsize)-1 1,20 1

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-194Software Interrupt 1 Control RegisterThe table below sho

4-20 Computer Group Literature Center Web SiteProgramming4Interrupt Base Vector RegisterThe table below shows the interrupt base vector register. Bit

Programming The Peripheral Channel Controllerhttp://www.motorola.com/computer/literature 4-214Software Interrupt 2 Control RegisterThe table below sho

4-22 Computer Group Literature Center Web SiteProgramming4Printer Status RegisterThe table below shows the printer status register. These bits are not

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-234Programming the LCSRThere are 14 LCSR registers as shown in the following tabl

4-24 Computer Group Literature Center Web SiteProgramming4VMEbus Requester Configuration RegisterThe table below shows the VMEbus requester configurat

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-254Master Configuration RegisterThe table below shows the master configuration re

4-26 Computer Group Literature Center Web SiteProgramming4Note While making it optional for the master to provide the UAT data transfer capability, th

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-274XTXX110 101110$2E0F1X001 111001$390F1X010 111010$3A0F1X101 111101$3D0F1X110 11

viiiCPU Address Space...3-7Coprocessor Register Map ...

4-28 Computer Group Literature Center Web SiteProgramming4Note The MC68030 is not notified via BERR* if an error occurs while the VMEchip is finishin

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-294Timer Configuration RegisterThe table below shows the timer configuration regi

4-30 Computer Group Literature Center Web SiteProgramming4Slave Address Modifier RegisterThe table below shows the slave address modifier register. AC

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-314This register allows software to configure which address modifier codes for th

4-32 Computer Group Literature Center Web SiteProgramming4Master Address Modifier RegisterThe table below shows the master address modifier register.

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-334Utility Interrupt Mask RegisterThe table below shows the utility interrupt mas

4-34 Computer Group Literature Center Web SiteProgramming4Utility Interrupt Vector RegisterThe table below shows the utility interrupt vector register

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-354Note The contents of the utility interrupt vector register must not be change

4-36 Computer Group Literature Center Web SiteProgramming4This register is used to configure the interrupt request line that the interrupter activates

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-374VMEbus Status/ID RegisterThe table below shows the VMEbus status/ID register.

ixSlave Base Address Register ...4-17Software Interrupt 1 Control Register...

4-38 Computer Group Literature Center Web SiteProgramming4This register allows software to set the base address of the GCSR set in the VMEbus supervis

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-394Programming the GCSRThere are eight GCSR registers as shown in the following t

4-40 Computer Group Literature Center Web SiteProgramming4Note The GCSR set must respond to VMEbus accesses for this function to be enabled. The MVME1

Programming the VMEchiphttp://www.motorola.com/computer/literature 4-414Note If the MVME147S sets its own R&H bit, it causes itself to be maintain

4-42 Computer Group Literature Center Web SiteProgramming4The MC68030 can both read and write to this register. The VMEbus can only read it. This regi

5-155Functional DescriptionIntroductionThis chapter provides the functional description of the MVME147S at block level. The functional description pro

5-2 Computer Group Literature Center Web SiteFunctional Description5MC68882 FPCThe MC68882 Floating-Point Coprocessor (FPC) is connected to the MC6803

Functional Descriptionhttp://www.motorola.com/computer/literature 5-35System Clock UtilityThe 16 MHz system clock is driven onto the VMEbus SYSCLK* si

5-4 Computer Group Literature Center Web SiteFunctional Description5VMEbus InterrupterThe VMEchip incorporates a flexible, multilevel bus interrupter

Functional Descriptionhttp://www.motorola.com/computer/literature 5-55write, read-modify- write, or interrupt acknowledge cycle, it requests the VMEch

xSystem Reset Function (SYSRESET*)...5-3VMEbus Interrupter ...

5-6 Computer Group Literature Center Web SiteFunctional Description5The requester maintains VMEbus mastership as long as one of the following conditio

Functional Descriptionhttp://www.motorola.com/computer/literature 5-75❏ Peripheral chip map decoder❏ Two programmable tick timers❏ Watchdog timer.❏ Pa

5-8 Computer Group Literature Center Web SiteFunctional Description5DMAC Operation StatesThe DMAC is always in one of three operational states: idle s

Functional Descriptionhttp://www.motorola.com/computer/literature 5-95Note The DMAC table must always be placed within 32-bit memory. The PCC termina

5-10 Computer Group Literature Center Web SiteFunctional Description5SCSI Chip InterfaceThe PCC provides the interface for MC68030 accesses of the WD3

Functional Descriptionhttp://www.motorola.com/computer/literature 5-115RESET and ABORT SwitchesThe PCC provides the RESET and ABORT switch interface.

5-12 Computer Group Literature Center Web SiteFunctional Description5The four serial ports on the MVME147S are different functionally because of the l

Functional Descriptionhttp://www.motorola.com/computer/literature 5-135Every MVME147S is assigned an Ethernet station address. The address is $08003E2

5-14 Computer Group Literature Center Web SiteFunctional Description5Battery Backed Up RAM and ClockThe Mostek MK48T02 RAM and clock chip is used on t

Functional Descriptionhttp://www.motorola.com/computer/literature 5-155Figure 5-1. Timings Required by the MVME147S2728 0004READVA L I DA0-A15CE*OE*D