Motorola MVME712AM Manuel de service

MVME162FXEmbedded ControllerProgrammer’sReference Guide V162FXA/PG1

VMEchip22-282Programming the VMEbus Slave Map DecodersThis section includes programming information for the VMEbus to local bus map decoders. The VMEb

LCSR Programming Model2-292and starting and ending address registers should be programmed first, and then the map decoders should be enabled by progra

VMEchip22-302enabled, the local bus address is generated by adding the offset value to the VMEbus address lines VA<31..16>. The offset is the va

LCSR Programming Model2-312VMEbus Slave Ending Address Register 1 This register is the ending address register for the first VMEbus to local bus map d

VMEchip22-322VMEbus Slave Starting Address Register 2 This register is the starting address register for the second VMEbus to local bus map decoder. V

LCSR Programming Model2-332VMEbus Slave Address Translation Select Register 1 This register is the address translation select register for the first V

VMEchip22-342VMEbus Slave Address Translation Address Offset Register 2This register is the address translation address register for the second VMEbus

LCSR Programming Model2-352VMEbus Slave Write Post and Snoop Control Register 2This register is the slave write post and snoop control register for th

VMEchip22-362VMEbus Slave Address Modifier Select Register 2This register is the address modifier select register for the second VMEbus to local bus ma

LCSR Programming Model2-372A32 When this bit is high, the second map decoder responds to VMEbus A32 (extended) access cycles. When this bit is low, th

xi Contents Chapter 1 Board Description and Memory Maps Introduction ...

VMEchip22-3821 Write - Sink data Read - Supply dirty data and leave dirty 2 Write - Invalidate Read - Supply dirty data and mark invalid 3 Snoop inhib

LCSR Programming Model2-392D64 When this bit is high, the first map decoder responds to VMEbus D64 block access cycles. When this bit is low, the firs

VMEchip22-402space. The second I/O map decoder provides an A24/D16 space at $F000000 to $F0FFFFFF and an A32/D16 space at $F1000000 to $FF7FFFFF. A pr

LCSR Programming Model2-412The address translation address register and the address translation select register operate in the following way. If a bit

VMEchip22-422Local Bus Slave (VMEbus Master) Ending Address Register 1This register is the ending address register for the first local bus to VMEbus m

LCSR Programming Model2-432Local Bus Slave (VMEbus Master) Starting Address Register 2This register is the starting address register for the second lo

VMEchip22-442Local Bus Slave (VMEbus Master) Ending Address Register 4 This register is the ending address register for the fourth local bus to VMEbus

LCSR Programming Model2-452Local Bus Slave (VMEbus Master) Address Translation Select Register 4 This register is the address translation select regis

VMEchip22-462Local Bus Slave (VMEbus Master) Attribute Register 3 This register is the attribute register for the third local bus to VMEbus bus map de

LCSR Programming Model2-472AM These bits define the VMEbus address modifier codes the VMEbus master uses for the segment defined by map decoder 2. Sin

xii DMAC Parity Error ... 1-43DMAC Off-board Error...

VMEchip22-482D16 When this bit is high, D16 data transfers are performed to the segment defined by map decoder 1. When this bit is low, D32 data trans

LCSR Programming Model2-492GCSR Board These bits define the board number portion of the GCSR address. These bits are compared with VMEbus address line

VMEchip22-502Local Bus to VMEbus I/O Control Register This register controls the VMEbus short I/O map and the F page ($F0000000 through $FF7FFFFF) I/O

LCSR Programming Model2-512I2SU When this bit is high, the VMEchip2 drives a supervisor address modifier code when the F page is accessed. When this b

2VMEchip22-522VMEchip22LCSR Programming ModelProgramming the VMEchip2 DMA ControllerThis section includes programming information on the DMA controlle

LCSR Programming Model2-532Once the DMAC is enabled, the counter and control registers should not be modified by software. When the command chaining m

VMEchip22-542PROM Decoder, SRAM and DMA Control Register This register controls the snoop control bits used by the DMAC when it is accessing table en

LCSR Programming Model2-552Local Bus to VMEbus Requester Control Register This register controls the VMEbus request level, the request mode, and relea

VMEchip22-562to the release mode programmed in the LVRWD bit. When the VMEbus has been acquired, the DHB bit is set. DHB When this bit is high, the VM

LCSR Programming Model2-5720 Release when the time on timer has expiredand a BRx* signal is active on the VMEbus. 1 Release when the time on timer has

xiii VMEbus Slave Ending Address Register 1 ... 2-31VMEbus Slave Starting Address Register 1 ...

VMEchip22-582D16 When this bit is high, the DMAC executes D16 cycles on the VMEbus. When this bit is low, the DMAC executes D32/D64 cycles on the VMEb

LCSR Programming Model2-592DMAC Control Register 2 (bits 0-7) This portion of the control register is loaded by the processor or the DMAC when it load

VMEchip22-6023 The DMAC executes D64 block transfercycles on the VMEbus. In the block transfermode, the DMAC may execute byte, two-byte and four-byte

LCSR Programming Model2-612DMAC VMEbus Address Counter In the direct mode, this counter is programmed with the starting address of the data in VMEbus

VMEchip22-622Table Address Counter In the command chaining mode, this counter should be loaded by the processor with the starting address of the list

LCSR Programming Model2-632is used. Normal VMEbus interrupts should never be cleared. This bit always reads 0 and writing a 0 to this bit has no effec

VMEchip22-642MPU Status and DMA Interrupt Count Register This is the MPU status register and DMAC interrupt counter. MLOB When this bit is set, the MP

LCSR Programming Model2-652DMAC Status Register This is the DMAC status register. DONE This bit is set when the DMAC has finished executing commands a

VMEchip22-662DLBE When this bit is set, the DMAC received a TEA and additional status was not provided. This bit is cleared when the DMAC is enabled.

LCSR Programming Model2-672DMAC Ton/Toff Timers and VMEbus Global Time-out Control RegisterThis register controls the DMAC time off timer, the DMAC ti

xiv DMAC Control Register 1 (bits 0-7) ... 2-56DMAC Control Register 2 (bits 8-15) ...

VMEchip22-682VME Access, Local Bus, and Watchdog Time-out Control Register WDTO These bits define the watchdog time-out period:LBTO These bits define

LCSR Programming Model2-692Prescaler Control Register The prescaler provides the various clocks required by the counters and timers in the VMEchip2. I

VMEchip22-702Tick Timer 1 Compare Register The tick timer 1 counter is compared to this register. When they are equal, an interrupt is sent to the loc

LCSR Programming Model2-712Tick Timer 2 Compare Register The tick timer 2 counter is compared to this register. When they are equal, an interrupt is s

VMEchip22-7220LCSR Programming ModelTick Timer 2 Compare Register The tick timer 2 counter is compared to this register. When they are equal, an inter

LCSR Programming Model2-732Board Control Register RSWE The RESET switch enable bit is used with the ÔÔno VMEbus interfaceÕÕ option. This bit is duplic

VMEchip22-742Watchdog Timer Control Register WDEN When this bit is high, the watchdog timer is enabled. When this bit is low, the watchdog timer is no

LCSR Programming Model2-752WDCS When this bit is set high, the watchdog time-out status bit (WDTO bit in this register) is cleared. SRST When this bit

VMEchip22-762Tick Timer 1 Control Register EN When this bit is high, the counter increments. When this bit is low, the counter does not increment. COC

2VMEchip22-772VMEchip2LCSR Programming ModelProgramming the Local Bus InterrupterThe local bus interrupter is used by devices that wish to interrupt t

xv Software Interrupt Set Register (bits 8-15)... 2-88Interrupt Clear Register (bits 24-31) ...

VMEchip22-782Table 2-3. Local Bus Interrupter Summary Interrupt VectorPriority forSimultaneous InterruptsVMEbus IRQ1 External LowestVMEbus IRQ2 Exter

LCSR Programming Model2-792Notes 1. X = The contents of vector base register 0. 2. Y = The contents of vector base register 1. 3. Refer to the Vector

VMEchip22-802Local Bus Interrupter Status Register (bits 24-31) This register is the local bus interrupter status register. When an interrupt status b

LCSR Programming Model2-812Local Bus Interrupter Status Register (bits 16-23) This register is the local bus interrupter status register. When an inte

VMEchip22-822Local Bus Interrupter Status Register (bits 8-15) This register is the local bus interrupter status register. When an interrupt status bi

LCSR Programming Model2-832Local Bus Interrupter Status Register (bits 0-7) This register is the local bus interrupter status register. When an interr

VMEchip22-842Local Bus Interrupter Enable Register (bits 24-31) This register is the local bus interrupter enable register. When an enable bit is high

LCSR Programming Model2-852Local Bus Interrupter Enable Register (bits 16-23) This register is the local bus interrupter enable register. When an enab

VMEchip22-862Local Bus Interrupter Enable Register (bits 8-15) This is the local bus interrupter enable register. When an enable bit is high, the corr

LCSR Programming Model2-872Local Bus Interrupter Enable Register (bits 0-7) This is the local bus interrupter enable register. When an enable bit is h

xvi Chapter 3 MC2 Chip Introduction ... 3-1Sum

VMEchip22-882Software Interrupt Set Register (bits 8-15) This register is used to set the software interrupts. An interrupt is set by writing a one to

LCSR Programming Model2-892CTIC2 Clear tick timer 2 interrupt CVI1E Clear VMEbus IRQ1 edge-sensitive interrupt CPE Not used on MVME162FXCMWP Clear VME

VMEchip22-902Interrupt Clear Register (bits 8-15) This register is used to clear the edge software interrupts. An interrupt is cleared by writing a on

LCSR Programming Model2-912Interrupt Level Register 1 (bits 16-23) This register is used to define the level of the SYSFAIL interrupt and the master w

VMEchip22-922Interrupt Level Register 1 (bits 0-7) This register is used to define the level of the tick timer 1 interrupt and the tick timer 2 interr

LCSR Programming Model2-932Interrupt Level Register 2 (bits 16-23) This register is used to define the level of the GCSR SIG2 interrupt and the GCSR S

VMEchip22-942Interrupt Level Register 2 (bits 0-7) This register is used to define the level of the GCSR LM0 interrupt and the GCSR LM1 interrupt. LM0

LCSR Programming Model2-952Interrupt Level Register 3 (bits 16-23) This register is used to define the level of the software 4 interrupt and the softw

VMEchip22-962Interrupt Level Register 3 (bits 0-7) This register is used to define the level of the software 0 interrupt and the software 1 interrupt.

LCSR Programming Model2-972Interrupt Level Register 4 (bits 16-23) This register is used to define the level of the VMEbus IRQ5 interrupt and the VMEb

xvii SRAM Space Base Address Register ... 3-27DRAM Space Size Register ...

VMEchip22-982Interrupt Level Register 4 (bits 0-7) This register is used to define the level of the VMEbus IRQ1 interrupt and the VMEbus IRQ2 interrup

LCSR Programming Model2-992I/O Control Register 1 This register is a general purpose I/O control register. Bits 16-19 control the direction of the fou

VMEchip22-1002I/O Control Register 2 This function is not used on the MVME162FX. I/O Control Register 3 This function is not used on the MVME162FX. Mi

LCSR Programming Model2-1012DISBSYT When this bit is low, the minimum VMEbus BBSY* time when the local bus master has been retried off the local bus i

VMEchip22-1022DISSRAM When this bit is high, the SRAM decoder in the VMEchip2 is disabled. When this bit is low, the SRAM decoder in the VMEchip2 is e

GCSR Programming Model2-1032GCSR Programming ModelThis section describes the programming model for the Global Control and Status Registers (GCSR) in t

VMEchip22-1042The chip ID and revision registers are provided to allow software to determine the ID of the chip and its revision level. The VMEchip2 h

GCSR Programming Model2-1052asserted, a local bus cycle may be aborted. The VMEchip2 is connected to both the local bus and the VMEbus and if the abor

VMEchip22-1062A summary of the GCSR is shown in Table 2-4. Table 2-4. VMEchip2 Memory Map (GCSR Summary)VMEchip2 GCSR Base Address = $FFF40100Offsets

GCSR Programming Model2-1072VMEchip2 Revision Register This register is the VMEchip2 revision register. The revision level for the VMEchip2 starts at

xviii Programming Model ... 4-10Chip ID Register ...

VMEchip22-1082SIG0 The SIG0 bit is set when a VMEbus master writes a one to it. When the SIG0 bit is set, an interrupt is sent to the local bus interr

GCSR Programming Model2-1092LM2 This bit is cleared by an LM2 cycle on the VMEbus. This bit is set when the local processor or a VMEbus master writes

VMEchip22-1102General Purpose Register 0 This register is a general purpose register that allows a local bus master to communicate with a VMEbus maste

GCSR Programming Model2-1112General Purpose Register 2 This register is a general purpose register that allows a local bus master to communicate with

VMEchip22-1122General Purpose Register 4 This register is a general purpose register that allows a local bus master to communicate with a VMEbus maste

33-13MC2 ChipIntroductionThe Memory Controller ASIC (MC2 chip) is one of three ASICs that are part of the MVME162FX hardware set. The MC2 chip is desi

MC2 Chip3-23Functional DescriptionThe following sections provide an overview of the functions provided by the MC2 chip. A detailed programming model f

Functional Description3-33The 28F008SA has a ready/busy pin to interrupt the processor when certain commands have completed. The MC2 chip does not uti

MC2 Chip3-43MPU Port access enables the MPU to write to an internal, 32-bit 82596CA command register. This allows the MPU to do four things: 1. Write

Functional Description3-53❏ Read ❏ Size ❏ Transfer in progress LANC Bus ErrorThe 82596CA does not provide a way to terminate a bus cycle with an error

Figures xix Figure 1-1. MVME162FX Block Diagram...1-5Figure 2-1. VMEchip2 Block Diagram...

MC2 Chip3-63SRAM Memory ControllerThe SRAM base address and size are programmable. The SRAM controller is designed to operate with 100 ns devices. The

Functional Description3-73Note TEA is the MC68040 bus error transaction signal. ÒWith TEAÓ indicates that a bus error cycle occurs if a DRAM parity er

MC2 Chip3-83Tick TimersThe MC2 chip implements four 32-bit tick timers. These timers are identical to the timers in the VMEchip2. The timers run on a

Memory Map of the MC2 chip Registers3-93Local Bus TimerThe MVME162FX provides a time-out function for the local bus. When the timer is enabled and a l

MC2 Chip3-103 Table 3-2. MC2 chip Register Map MC2 chip Base Address = $FFF42000Offset D31-D24 D23-D16 D15-D8 D7-D0$00 MC2 chip ID MC2 chipRevisionG

Programming Model3-113Programming ModelThis section defines the programming model for the control and status registers (CSR) in the MC2 chip. The base

MC2 Chip3-123MC2 chip Revision Register RV7-RV0 The current value of the chip revision is $01. This register is read only. It ignores a write but ends

Programming Model3-133MIEN Master Interrupt Enable. When this bit is high, interrupts from and via the MC2 chip are allowed to reach the MPU. When it

MC2 Chip3-143Interrupt Vector Base RegisterThe interrupt vector base register is an 8-bit read/write register that is used to supply the vector to the

Programming Model3-153 Note The Z85230 controller has an integrated interrupt vector register which is separate from the vector generation found on th

Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omiss

xx

MC2 Chip3-163Programming the Tick Timers There are four programmable tick timers in the MC2 chip. These timers are identical in function to the timers

Programming Model3-173Tick Timer 1 Compare Register Tick Timer 1 Counter Tick Timer 2 Compare Register Tick Timer 2 Counter ADR/SIZ $FFF42004 (32 bits

MC2 Chip3-183LSB Prescaler Count RegisterThis register is used to generate the 1 MHz clock for the four tick timers. This register is read-only. It in

Programming Model3-193Tick Timer 1 and 2 Control RegistersEach tick timer has a control register. The control registers for one and two are defined in

MC2 Chip3-203OVF3-OVF0 These bits are the output of the overflow counter. The overflow counter is incremented each time the tick timer sends an interr

Programming Model3-213Tick Timer Interrupt Control RegistersThere are four tick timer interrupt control registers. The register format is the same for

MC2 Chip3-223IL2-IL0 These three bits select the interrupt level for the tick timers. Level 0 does not generate an interrupt. ICLR Writing a logic 1

Programming Model3-233DRAM Parity Error Interrupt Control RegisterThe DRAM Parity Error Interrupt Control Register controls the interrupt logic for pa

MC2 Chip3-243SCC Interrupt Control Register IL2-IL0 These three bits select the interrupt level for the SCC controller. Level 0 does not generate an i

Programming Model3-253Tick Timer 3 and 4 Control RegistersTick Timer 4 Control Register Tick Timer 3 Control Register CEN When this bit is high, the c

xxi Tables Table 1-1. Redundant Functions in the VMEchip2 and MC2 chip...1-6Table 1-2. Local Bus Memory Map ...

MC2 Chip3-263DRAM and SRAM Memory Controller RegistersThe DRAM decode logic consists of a base register, a size register, and an options register. The

Programming Model3-273SRAM Space Base Address Register B31-B17 B31 - B17 are compared to local bus address signals A31 - A17 for memory reference cycl

MC2 Chip3-283DRAM Space Size Register DZ2-DZ0 The size bits configure the DRAM decoder for a particular memory size. The following table defines their

Programming Model3-293DRAM/SRAM Options RegisterNote that this register is read only and is initialized at reset. DZ2-DZ0 DZx bits indicate the size a

MC2 Chip3-303SZ1-SZ0 SZx bits indicate the size of the SRAM array. Software must initialize the SRAM Space Size Register ($FFF42024 bits 9 - 8) based

Programming Model3-313SRAM Space Size Register SEN SRAM ENABLE must be set to a one before the SRAM can be accessed. SZ1-SZ0 The size bits configure t

MC2 Chip3-323LANC Error Status Register SCLR Writing a 1 to this bit clears bits LTO,EXT, and PRTY. Reading this bit always yields 0. LTO,EXT, These b

Programming Model3-33382596CA LANC Interrupt Control Register IL2-IL0 Interrupt Request Level. These three bits select the interrupt level for the 825

MC2 Chip3-343LANC Bus Error Interrupt Control Register IL2-IL0 Interrupt Request Level. These three bits select the interrupt level for the 82596CA LA

Programming Model3-353SCSI Error Status Register SCLR Writing a 1 to this bit clears bits LTO, EXT, and PRTY. Reading this bit always yields 0. LTO,EX

xxii

MC2 Chip3-363General Purpose Inputs RegisterThe contents of a PAL and the state of an 8-position jumper block are translated to bit settings of the Ge

Programming Model3-373MVME162FX Version RegisterThe contents of a PAL and the state of an 8-position jumper block are translated to bit settings of th

MC2 Chip3-383V7 Reserved for internal use only. (V7 is set to a 1 indicating that the IP2 chip #1 is present.)SCSI Interrupt Control Register IL2-IL0

Programming Model3-393Tick Timer 3 and 4 Compare and Counter RegistersTick timers three and four are defined here because they maintain this relative

MC2 Chip3-403Tick Timer 4 CounterBus Clock RegisterThe Bus Clock Register should be programmed with the hexadecimal value of the operating clock frequ

Programming Model3-413EPROM Access Time Control RegisterThe MVME162FX is populated with a 150ns EPROM memory device. Due to the wide range of EPROM sp

MC2 Chip3-423Flash Parameter RegisterThe MVME162FX is populated with a 120ns Flash memory device. Due to the wide range of Flash speeds, the contents

Programming Model3-433ABORT Switch Interrupt Control RegisterThe following table describes the ABORT switch interrupt logic in the MC2 chip.IL2-IL0 Th

MC2 Chip3-443RESET Switch Control RegisterThe RESET switch on the MVME162FX front panel and several status and control bits are defined by this regist

Programming Model3-453Watchdog Timer Control RegisterThe watchdog timer control logic in the MC2 chip is used with the ÒNo VMEbus InterfaceÓ option. T

1 1-1 1Board Descriptionand Memory Maps Introduction This manual provides programming information for the MVME162FX Embedded Controller. Extensive pr

MC2 Chip3-463Access and Watchdog Time Base Select RegisterThe watchdog timer control logic in the MC2 chip is used with the ÒNo VMEbus InterfaceÓ opti

Programming Model3-473DRAM Control RegisterThis register controls the parity checking mode and DRAM enable.Note Do not enable parity unless it is supp

MC2 Chip3-483WWP Setting WWP to a one causes inverted parity to be written to the DRAM. This is used for diagnostic software.

Programming Model3-493MPU Status RegisterThis logic is duplicated in the VMEchip2 at location $FFF40048, bits 11, 10, 9, and 7. The duplication is to

MC2 Chip3-50332-bit Prescaler Count RegisterThe prescaler register is used to clock timing functions in the MC2 chip. The lower 8 bits of the prescale

44-14IP2 ChipIntroductionThis chapter describes the IndustryPack Interface Controller (IP2 chip) ASIC for the MC68040 bus. The IP2 chip is designed fo

IP2 Chipming Model4-24❏ Recovery timer for each IndustryPack to provide dead time between back to back accesses. Functional DescriptionThe following s

Functional Description4-34Local Bus to IndustryPack DMA ControllersThe IP2 supports two basic types of DMA cycles: Òstandard DMAÓ (sDMA) and Òaddresse

IP2 Chipming Model4-44and destination addresses are not aligned, so the local bus and the IndustryPack can operate at their maximum data transfer size

Functional Description4-54Clocking Environments and PerformanceThe IP2 chip has two clock domains. The majority of the logic is controlled by the MC68

Board Description and Memory Maps1-21 (IP) interfaces with DMA, SCSI bus interface with DMA, VMEbus controller, and 512KB of SRAM with battery backup

IP2 Chipming Model4-64Notes 1. This column is a measure of IndustryPack bandwidth for back to back cycles for a local bus master which is accessing a

Functional Description4-74reverse the polarity of the pacer clock output. The pacer clock outputÕs programmable frequency range is from approximately

IP2 Chipming Model4-84InterruptsThe IP2 chip can be programmed to interrupt the local bus master via the IPL* signal pins when one or more of the eigh

Overall Memory Map4-94Overall Memory MapThe following memory map table includes all devices selected by the IP2 chip map decoder. Table 4-2. IP2 chip

IP2 Chipming Model4-104Programming ModelThis section defines the programming model for the control and status registers (CSRs) in the IP2 chip. The ba

Programming Model4-114Table 4-3. IP2 chip Memory Map - Control and Status Registers IP2 chip Base Address = $FFFBC000Register OffsetRegister NameReg

IP2 Chipming Model4-124$18 IP_a GENERAL CONTROLa_ERR 0 a_RT1 a_RT0 a_WIDTH1 a_WIDTH0 a_BTD a_MEN$19 IP_b GENERAL CONTROLb_ERR 0 b_RT1 b_RT0 b_WIDTH1 b

Programming Model4-134DMAC for IndustryPack a, request 0. This register set is referred to as DMACa in the text.$20 DMA_a STATUS 0 DLBE 0 IPEND CHANI

IP2 Chipming Model4-144DMAC for IndustryPack b, request 0 or for IndustryPack a, request 1. This register set is referred to as DMACb in the text.$38

Programming Model4-154DMAC for IndustryPack c, request 0. This register set is referred to as DMACc in the text.$50 DMA_c STATUS 0 DLBE 0 IPEND CHANI

Introduction1-31 The IndustryPack Interface Controller (IP2 chip) ASIC provides control and status information, including DMA control, for up to four

IP2 Chipming Model4-164DMAC for IndustryPack d, request 0 or for IndustryPack c, request 1, and for PACER CLOCK. This register set, not including the

Programming Model4-174Chip ID RegisterThe read-only Chip ID Register is hard-wired to a hexadecimal value of $23. Writes to this register do nothing,

IP2 Chipming Model4-184Vector Base RegisterThe interrupt Vector Base Register is an 8-bit read/write register that is used to supply the vector to the

Programming Model4-194A normal read access to the Vector Base Register yields the value $0F if the read happens before it has been initialized. A norm

IP2 Chipming Model4-204$00060000, etc. If both a_SIZE16 and a_SIZE17 were set, then the base address for IP_a could be programmed for one of $00000000

Programming Model4-214IP_c or Double Size IP_cd Memory Base Address Registers (not used on MVME162LX)IP_d Memory Base Address Registers (not used on M

IP2 Chipming Model4-224IP_a, IP_b, IP_c, IP_d Memory Size RegistersAs with the memory base address registers, the IP_a size register is also used to c

Programming Model4-234IP_a, IP_b, IP_c, and IP_d; IRQ0 and IRQ1 Interrupt Control Registers IL2-IL0 These three bits select the interrupt level for th

IP2 Chipming Model4-244rising edge/high level of the IndustryPack IRQ*. Note that if this bit is changed while the E/L* bit is set (or is being set),

Programming Model4-254IP_a, IP_b, IP_c, and IP_d; General Control Registers MEN a_MEN/b_MEN/c_MEN/d_ MEN enable the local bus to perform read/write ac

Board Description and Memory Maps1-41 ❏ Watchdog timer ❏ Eight software interrupts (for MVME162FX versions that have the VMEchip2) ❏ I/O Ð Two seri

IP2 Chipming Model4-264DMA function because they are the only cycles which can occur back to back. When BTD is set to a zero, the IndustryPack interfa

Programming Model4-274or 16-bits, c_WIDTH1-c_WIDTH0 must be programmed for one of 8-bits or 16-bits. This applies whether or not c_MEN is set. RT1,RT0

IP2 Chipming Model4-284followed by a double size I/O access, the double size access may be allowed to happen before the recovery times for both a and

Programming Model4-294IP Clock RegisterIP32 Setting IP32 to a 1 enables the IndustryPack bus to operate synchronously with the MC68040 local bus clock

IP2 Chipming Model4-304DMA Arbitration Control RegisterThe DMA arbitration control register contents determine whether a fixed or fair arbitration alg

Programming Model4-314IP RESET Register RES Setting RES to a one asserts the IP2 chip IPRESET* signal. IPRESET* is intended to be connected to the Res

IP2 Chipming Model4-324Each DMAC has two modes of operation: command chaining, and direct. In the direct mode, the local bus address, the IndustryPack

Programming Model4-334Once a DMAC is enabled, its counter and control registers should not be modified by software. When the command chaining mode is

IP2 Chipming Model4-344The following are legal contexts for DMA channel configurations. Note that configuration rules for DMA controllers for IP_a and

Programming Model4-354DMA Status RegisterDONE This bit is set when DMAC has finished executing commands and there were no errors, or DMAC has finished

Block Diagram1-51Block DiagramFigure 1-1 is a general block diagram of the MVME162FX. Figure 1-1. MVME162FX Block DiagramFunctional DescriptionThis

IP2 Chipming Model4-364bit was detected in the DMA Control Register 1. A DMAC interrupt will be generated if interrupts are enabled.IPEND When this bi

Programming Model4-374DMA Enable RegisterDEN Setting the DEN bit to a one will enable the DMA function. Software should not write to the DMA control r

IP2 Chipming Model4-384DMA Control Register 1XXX This bit must remain cleared. If it is set to a one, the IP2 chip ASIC will not function correctly.A_

Programming Model4-394unlike the width control bits in the General Control Registers, these width control bits define the width of both the memory and

IP2 Chipming Model4-404DMA Control Register 2This register is loaded by the processor or by DMA when it loads the command word from the command packet

Programming Model4-414DMAEO When DMAEO is set, DMA drives DMAEND and asserts it during the DMA IP cycle in which the byte count expires. When DMAEO is

IP2 Chipming Model4-424DMA IndustryPack Address CounterIn the direct mode, this counter is programmed with the starting address of the data buffer in

Programming Model4-434DMA Table Address CounterIn the command chaining mode, this counter should be loaded by the processor with the starting address

IP2 Chipming Model4-444Programming the Pacer ClockPacer clock registers are defined in the following paragraphs.Pacer Clock Interrupt Control Register

Programming Model4-454Pacer Clock General Control RegisterPS2-0 These three bits select the frequency of the pre-scale logic output The MC68040 bus cl

Board Description and Memory Maps1-61No-VMEbus-Interface OptionThe MVME162FX can be operated as an embedded controller without the VMEbus interface. F

IP2 Chipming Model4-464EN When the EN bit is set, the pacer clock is enabled. When it is cleared, the pacer clock is suspended. EN performs its functi

Local Bus to IndustryPack Addressing4-474Local Bus to IndustryPack AddressingThe following sections provide examples that illustrate local bus versus

IP2 Chipming Model4-48416-Bit Memory SpaceThis example is for IP_a, where the IP_a memory space is programmed with a base address of $00000000, a size

Local Bus to IndustryPack Addressing4-49432-Bit Memory SpaceThis example is for IP_ab, where the IP_ab memory space is programmed with a base address

IP2 Chipming Model4-504IP_a I/O SpaceThis example is for IP_a I/O space. The relationship of the IndustryPack address to the local bus address is: IPA

Local Bus to IndustryPack Addressing4-514IP_ab I/O SpaceThis example is for 32-bit, IP_ab I/O space. The relationship of the IndustryPack address to t

IP2 Chipming Model4-524IP_a ID SpaceThis example is for IP_a ID space. The relationship of the IndustryPack address to the local bus address is: IPA&l

IP to Local Bus Data Routing4-534IP to Local Bus Data RoutingThis section shows data routing from an IP to the local bus. Memory Space AccessesThe fol

IP2 Chipming Model4-544 IPWIDTH LBSIZE LBA IPA LD<31-24> LD<23-16> LD<15-8> LD<7-0>8 BitsBYTE 0 1 IPXD<7-0>13 IPXD<7-

IP to Local Bus Data Routing4-554I/O and ID Space AccessesThe following table shows the data routing when accessing IP I/O or ID space. SPACE refers t

Functional Description1-71Notes 1. RESET switch control.2. Watchdog timer control.3. Access and watchdog timer parameters.4. MPU TEA (bus error) statu

IP2 Chipming Model4-564

55-15Serial Port ConnectionsIntroductionThis chapter contains connection diagrams for Serial Ports 1 and 2 on the MVME162FX. (Serial Port 2 uses Seria

Serial Port Connections5-25and MVME712B Transition Modules and LCP2 Adapter Board User's Manual or the MVME712M Transition Module and P2 Adapter

Introduction5-35Figure 5-1. MVME162FX Port 1 EIA-232 DCE, MVME712M Port 2 DTEFRONT PANEL+12VP2-C27P2-C28P2-C29P2-C30P2-C31P2-C32TXD2RXD2RTS2CTS2DTR2D

Serial Port Connections5-45Figure 5-2. MVME162FX Port 1 EIA-232 DCE, MVME712M Port 2 DCEFRONT PANEL+12VP2-C27P2-C28P2-C29P2-C30P2-C31P2-C32TXD2RXD2RT

Introduction5-55Figure 5-3. MVME162FX Port 2 EIA-232 DTE, MVME712M Port 4 DTEFRONT PANEL+12VP2-A25P2-A26P2-A27P2-A29P2-A30P2-A31TXD4RXD4RTS4CTS4DTR4D

Serial Port Connections5-65Figure 5-4. MVME162FX Port 2 EIA-232 DCE, MVME712M Port 4 DCEFRONT PANEL+12VP2-A25P2-A26P2-A27P2-A29P2-A30P2-A31TXD4RXD4RT

Introduction5-75Figure 5-5. MVME162FX Port 2 EIA-232 DTE, MVME712M Port 4 DCEFRONT PANEL+12VP2-A25P2-A26P2-A27P2-A29P2-A30P2-A31TXD4RXD4RTS4CTS4DTR4D

Serial Port Connections5-85Figure 5-6. MVME162FX Port 2 EIA-232 DCE, MVME712M Port 4 DTEFRONT PANEL+12VP2-A25P2-A26P2-A27P2-A29P2-A30P2-A31TXD4RXD4RT

Introduction5-95Figure 5-7. MVME162FX Port 2 EIA-530 DTE10971.00 (1-2) 94054TXD_BTXD_ARXD_BRXD_ARTS_BRTS_ACTS_BCTS_ADTR_BDTR_ADCD_BDCD_ADSR_BDSR_ATXC

Preface This manual provides board level information and detailed ASIC chip information including register bit descriptions for the MVME162FX Embedd

Board Description and Memory Maps1-81Note that the ABORT switch logic in the VMEchip2 is not used. The GPI inputs to the VMEchip2, which are located a

Serial Port Connections5-105Figure 5-8. MVME162FX Port 2 EIA-530 DCE10971.00 (2-2) 94054TXD_BTXD_ARXD_BRXD_ARTS_BRTS_ACTS_BCTS_ADTR_BDTR_ADCD_BDCD_AD

Introduction5-115Figure 5-9. MVME162FX Port 1 EIA-232 DCE, MVME712A/AM/-12/-13 Port 2DTEFRONT PANEL+12VP2-C27P2-C28P2-C29P2-C30P2-C31P2-C32TXD2RXD2RT

Serial Port Connections5-125Figure 5-10. MVME162FX Port 1 EIA-232 DCE, MVME712AM/-13 Port 2 asModem Port+12VTXDRXDRTSCTSDTRDCD1.5KSERIAL PORT 2MODEM

Introduction5-135Figure 5-11. MVME162FX Port 2 EIA-232 DTE, MVME712A/AM/-12/-13 Port 4DTE+12VTXDRXDRTSCTSDTRDCD1.5KMVME 712A/AM/-12/-13 PORT 4 (DTE)7

Serial Port Connections5-145Figure 5-12. MVME162FX Port 2 EIA-232 DCE, MVME712A/AM/-12/-13 Port 4DTE+12VTXDRXDRTSCTSDTRDCD1.5KMVME 712A/AM/-12/-13 PO

Introduction5-155Figure 5-13. MVME162FX EIA-485/EIA-422 Connections1566 9501TXD_BTXD_ARXD_BRXD_ATXC_BTXC_ARXC_BRXC_ATXD_BTXD_ARXD_BRXD_ATXC_BTXC_ARXC

Serial Port Connections5-165

AA-1AUsing Interrupts onthe MVME162FXIntroductionThis appendix demonstrates how to use interrupts on the MVME162FX. It gives an example of how to gene

Using Interrupts on the MVME162FXA-2AB. Set up local bus interrupter.4. Tick Timer 1 Control Register $FFF40060 (8 bits) Write $07 to this register (s

VMEchip2 Tick Timer 1 Periodic Interrupt ExampleA-3APeriodic Tick Timer 1 interrupts now occur, so you need an interrupt handler. Section C gives the

Memory Maps1-91 Table 1-2. Local Bus Memory MapAddress Range Devices Accessed Port Width SizeSoftware Cache InhibitNote(s)Programmable DRAM on board

Using Interrupts on the MVME162FXA-4A

IndexIN-1Numerics28F008SA 3-328F008SA data sheet vii53C710 data sheet vii53C710 interface, MC2 chip 3-582596CA 3-3, 3-33, 3-3482596CA data sheet

IndexIN-2INDEXboard failure 2-73board ID 1-35Board Status/Control Register, VMEchip2 2-109BRDFAIL signal pin 2-73, 2-74broadcast interrupt functio

IndexIN-3INDEXdollar sign, definition ivDRAM Control Register, MC2 chip 3-47DRAM controller 3-1DRAM enable 3-47DRAM memory controller, MC2 chip 3

IndexIN-4INDEXGeneral Purpose Register 5 2-112general purpose registers 2-104generate clock for tick timers 3-18Global Control and Status Registers

IndexIN-5INDEXlocal bus to IndustryPack addressing 4-47overall memory map 4-9programming model 4-10IP2 chip overall memory map 1-22IRQ0, IRQ1 Inte

IndexIN-6INDEXDMA controller, VMEchip2 2-11interface 2-4interface, VMEchip2 2-4map decoders, programming 2-39requester 2-8requester register, pro

IndexIN-7INDEXMVME162FX Version Register, MC2 chip 3-37MVME712X 1-2MVME712x 5-1Nnegation, definition ivno address increment DMA transfers 2-13non

IndexIN-8INDEXVMEchip2 2-107ROM Control Register 2-51ROM0 bit 2-54Round Robin Select (RRS) mode 2-18SSCC interface, MC2 chip 3-1, 3-7SCC Interrup

IndexIN-9INDEXTick Timer 1 Counter 2-70, 3-17Tick Timer 2 Compare Register 2-71, 3-17Tick Timer 2 Control Register 2-75Tick Timer 2 Counter 2-71,

Board Description and Memory Maps1-101Notes1. Reset enables the decoder for this space of the memory map so that it will decode address spaces $FF8000

IndexIN-10INDEXVMEbus system controller, VMEchip2 2-18VMEbus timer 2-19VMEbus to local bus interface 2-9VMEchip2block diagram 2-5functional blocks

Memory Maps1-111The following table focuses on the Local I/O Devices portion of the local bus Main Memory Map. Table 1-3. Local Bus I/O Devices Memor

Board Description and Memory Maps1-121$FFF58A00 - $FFF58A7F Reserved -- 128B 1$FFF58A80 - $FFF58AFF Reserved -- 128B 1$FFF58B00 - $FFF58B7F Reserved -

Memory Maps1-131Notes 1. For a complete description of the register bits, refer to the data sheet for the specific chip. For a more detailed memory ma

Board Description and Memory Maps1-141Note ManufacturersÕ errata sheets for the various chips are available by contacting your local Motorola sales re

Memory Maps1-151Table 1-4. VMEchip2 Memory Map (Sheet 1 of 3)DMA TBSNP MODEROMZEROSRAMSPEEDADDER2SLAVE ENDING ADDRESS 1SLAVE ENDING ADDRESS 2SLAVE AD

Board Description and Memory Maps1-161This sheet begins on facing page.ARBROBNMASTDHBMASTDWBMSTFAIRMSTRWDMASTERVMEBUSDMAHALTDMAENDMATBLDMAFAIRDMRELMDM

Memory Maps1-171Table 1-4. VMEchip2 Memory Map (Sheet 2 of 3)ENIRQ31ENIRQ30ENIRQ29ENIRQ28ENIRQ27ENIRQ26ENIRQ25ENIRQ24ENIRQ23ENIRQ22ENIRQ21ENIRQ20ENIR

Manual Terminology Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric for

Board Description and Memory Maps1-181

Memory Maps1-191This sheet begins on facing page.0123456789101112131415VMEACCESSTIMERLOCALBUSTIMERWD TIME OUTSELECTPRESCALERCLOCK ADJUSTTICEN1COCEN1CL

Board Description and Memory Maps1-201Table 1-4. VMEchip2 Memory Map (Sheet 3 of 3) VMEchip2 GCSR Base Address = $FFF40100Offsets Bit NumbersVME-busL

Memory Maps1-211Table 1-5. MC2 chip Register MapMC2 chip Base Address = $FFF42000 Offset D31-D24 D23-D16 D15-D8 D7-D0$00 MC2 chip ID MC2 chipRevision

Board Description and Memory Maps1-221The following memory map table includes all devices selected by the IP2 chip map decoder. A summary of the IP2 c

Memory Maps1-231 Table 1-7. IP2 chip Memory Map - Control and Status Registers IP2 chip Base Address = $FFFBC000Register OffsetRegister NameRegister

Board Description and Memory Maps1-241$18 IP_a GENERAL CONTROLa_ERR 0 a_RT1 a_RT0 a_WIDTH1 a_WIDTH0 a_BTD a_MEN$19 IP_b GENERAL CONTROLb_ERR 0 b_RT1 b

Memory Maps1-251DMAC for IndustryPack a, request 0. This register set is referred to as DMACa in the text.$20 DMA_a STATUS 0 DLBE 0 IPEND CHANI TBL IP

Board Description and Memory Maps1-261DMAC for IndustryPack b, request 0 or for IndustryPack a, request 1. This register set is referred to as DMACb i

Memory Maps1-271DMAC for IndustryPack c, request 0. This register set is referred to as DMACc in the text.$50 DMA_c STATUS 0 DLBE 0 IPEND CHANI TBL IP

The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., Þrst published 1990, and may be us

Board Description and Memory Maps1-281DMAC for IndustryPack d, request 0 or for IndustryPack c, request 1, and for PACER CLOCK. This register set, not

Memory Maps1-291$80 PACER INT CONTROL0 IRE INT IEN ICLR IL2 IL1 IL0$81 PACER GEN CONTROLPLTY PLS 0 EN CLR PS2 PS1 PS0$82 PACER TIMERT15 T14 T13 T12 T1

Board Description and Memory Maps1-301Note A bug in MVME162FXs that have MC2 chip revision $01 does not allow the data registers to be accessed direct

Memory Maps1-311 Note Accesses may be 8-bit or 32-bit, but not 16-bit. BBRAM/TOD Clock Memory MapThe MK48T08 BBRAM (also called Non-Volatile RAM or NV

Board Description and Memory Maps1-321Table 1-11. MK48T08 BBRAM/TOD Clock Memory MapAddress Range Description Size (Bytes)$FFFC0000 - $FFFC0FFF User

Memory Maps1-331Notes W = Write Bit R = Read Bit S = Signbit ST = Stop Bit FT = Frequency Test x = Unused$FFFC1F86 - $FFFC1F8D IP c Board ID 8$FFF

Board Description and Memory Maps1-341The data structure of the configuration bytes starts at $FFFC1EF8 and is as follows. struct brdi_cnfg {char ver

Memory Maps1-351000000470476 3. Sixteen bytes are reserved for the board ID in ASCII format. For example, for an MVME162FX board with MC68040, SCSI, E

Board Description and Memory Maps1-36110. Eight bytes are reserved for the serial number assigned to the memory mezzanine board in ASCII format. 11. E

Software Support Considerations1-3710Software Support Considerations24. Eight bytes are reserved for the printed wiring board (PWB) number assigned to

Related Documentation The publications in the table below are applicable to the MVME162FX and may provide additional helpful information. If not ship

Board Description and Memory Maps1-381Software Support ConsiderationsThe MVME162FX is a complex board that interfaces to the VMEbus and SCSI bus. Thes

Software Support Considerations1-391processors is kept in memory that is not cached. The software must also mark all onboard and off-board I/O areas a

Board Description and Memory Maps1-401software accesses a nonexistent device within the VMEbus range, incorrect configuration information causes the V

Software Support Considerations1-411Description of Error Conditions on the MVME162FXThis section list the various error conditions that are reported b

Board Description and Memory Maps1-421Status:Bit 8 of the MPU Status and DMA Interrupt Count Register. Address $FFF40048.Comments:This can be caused b

Software Support Considerations1-431DMAC VMEbus ErrorDescription:The DMAC experienced a VMEbus error during an attempted transfer.MPU Notification:DMA

Board Description and Memory Maps1-441DMAC Off-board ErrorDescription:Error encountered while the local bus side of the DMAC was attempting to go to t

Software Support Considerations1-451DMAC TEA - Cause UnidentifiedDescription:An error occurred while the DMAC was local bus master and additional statu

Board Description and Memory Maps1-461LAN Off-board ErrorDescription:Error encountered while the LANCE was attempting to go to the VMEbus.MPU Notifica

Software Support Considerations1-471Description:Parity error detected while the 53C710 was reading DRAM.MPU Notification:53C710 Interrupt.Status:53C71

The following publications are also available from the sources indicated. Versatile Backplane Bus: VMEbus , ANSI/IEEE Std 1014-1987, The Institute o

Board Description and Memory Maps1-481Status:53C710 DMA Status Register 53C710 DMA Interrupt Status Register MC2 chip SCSI Error Status Register ($FFF

Software Support Considerations1-491has been granted. Because we have found in the past that some VME systems can become very busy, we recommend this

Board Description and Memory Maps1-501which start onboard and then access off-board resources. The MVME162FX does not fully support all RMW operations

22-12VMEchip2IntroductionThis chapter defines the VMEchip2 ASIC, local bus to VMEbus interface chip. The VMEchip2 interfaces the local bus to the VMEb

VMEchip22-22❏ VMEbus Bus to Local Bus Interface: Ð Programmable VMEbus map decoder. Ð Programmable AM decoder. Ð Programmable local bus snoop enable.

Introduction2-32Release-On-End-Of-Data (ROEOD); Software-configured BR0-BR3 request levels; andSoftware enabled bus-tenure timer. ❏ VMEbus Interrupter

VMEchip22-42Functional BlocksThe following sections provide an overview of the functions provided by the VMEchip2. See Figure 2-1 for a block diagram

Functional Blocks2-52Figure 2-1. VMEchip2 Block Diagram1344 9403DATACONTROLADDRESSCONTROLDATACONTROLADDRESSDATACONTROLADDRESSDATACONTROLADDRESSDATACO

VMEchip22-62Using programmable map decoders with programmable attribute bits, the local bus to VMEbus interface can be configured to provide the follo

Functional Blocks2-72When write posting is enabled, the VMEchip2 stores the local bus address and data and then acknowledges the local bus master. The

VMEchip22-82VMEbus. If the data transfer does not begin before the timer times out, the timer drives the local bus error signal, and sets the appropri

Functional Blocks2-92The local bus to VMEbus requester in the VMEchip2 implements a fair mode. By setting the LVFAIR bit, the requester refrains from

VMEchip22-102Adhering to the IEEE 1014-87 VMEbus Standard, the slave can withstand address-only cycles, as well as address pipelining, and respond to

Functional Blocks2-112The alternate address register also provides the upper eight bits of the local address when the VMEbus slave cycle is A24. The l

VMEchip22-122Data transfer capabilities: D16, D32, D16/BLT, D32/BLT,D64/BLT (BLT = block transfer) Using the DMA AM control register, the address modi

Functional Blocks2-132chaining mode is enabled, the DMAC reads and executes commands from the list in local memory until all commands are executed. Th

VMEchip22-142support the various port sizes and to allow transfers which are not an even byte count or start at an odd address, with respect to the po

Functional Blocks2-152Requiring no external jumpers, the chip provides the means for software to program the DMAC requester to request the bus on any

VMEchip22-162Software is required to load the appropriate constant, depending upon the local bus clock, following reset to ensure proper operation of

Functional Blocks2-172Watchdog TimerThe watchdog timer has a 4-bit counter, four clock select bits, an enable bit, a local reset enable bit, a SYSRESE

© Copyright Motorola, Inc. 1996All Rights ReservedPrinted in the United States of AmericaAugust 1996

VMEchip22-182should be enabled. All boards in the system which are not participating in the broadcast interrupt function should not drive or respond t

Functional Blocks2-192IACK Daisy-Chain DriverComplying with the latest revision of the VMEbus specification, the System Controller includes an IACK Da

VMEchip22-202Local Bus Interrupter and Interrupt HandlerThere are 31 interrupt sources in the VMEchip2: VMEbus ACFAIL, ABORT switch, VMEbus SYSFAIL, w

Functional Blocks2-212The DMAC interrupter is an edge-sensitive interrupter connected to the DMAC. The GCSR SIG3-0 interrupters are edge-sensitive int

VMEchip22-222Global Control and Status RegistersThe VMEchip2 includes a set of registers that are accessible from both the VMEbus and the local bus. T

LCSR Programming Model2-232❏ Line 4 defines the operations possible on the register bits as follows: ❏ Line 5 defines the state of the bit following a

VMEchip22-242Table 2-1. VMEchip2 Memory Map - LCSR Summary (Sheet 1 of 2)DMA TBSNP MODEROMZEROSRAMSPEEDADDER2SLAVE ENDING ADDRESS 1SLAVE ENDING ADDRE

LCSR Programming Model2-252ARBROBNMASTDHBMASTDWBMSTFAIRMSTRWDMASTERVMEBUSDMAHALTDMAENDMATBLDMAFAIRDMRELMDMAVMEBUSADDER1MASTWPENMASTWPENMASTD16ENMASTD1

VMEchip22-262Table 2-1. VMEchip2 Memory Map - LCSR Summary (Sheet 2 of 2)ENIRQ31ENIRQ30ENIRQ29ENIRQ28ENIRQ27ENIRQ26ENIRQ25ENIRQ24ENIRQ23ENIRQ22ENIRQ2

LCSR Programming Model2-272This sheet begins on facing page.0123456789101112131415VMEACCESSTIMERLOCALBUSTIMERWD TIME OUTSELECTPRESCALERCLOCK ADJUSTTIC