Motorola MVME712A/D3 Manuel d'utilisateur

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Page 1 - (MVME167BUG/D3)

MVME167BUG167Bug Debugging PackageUser's Manual (MVME167BUG/D3)

Page 2 - Restricted Rights Legend

List of Figures Flow Diagram of Board Operational Mode (Sheet 1 of 4) 1-3Flow Diagram of 166Bug/167Bug System Operational Mode 1-7Flow Diagram of 166

Page 3

Test Descriptions3-56 167Bug Debugging Package UserÕs Manual3This allows you to override the default address ranges for testing, on a per board basis.

Page 4

ECC Memory Board (MCECC) TestsMVME167BUG/D3 3-573Check-Bit DRAM - CBITThis test verifies the operation of the check-bit RAM. The test uses the addres

Page 5 - Contents

Test Descriptions3-58 167Bug Debugging Package UserÕs Manual3Failures in checkbit memory: At: ________, read: ________, should be: ________, (lower

Page 6

ECC Memory Board (MCECC) TestsMVME167BUG/D3 3-593Exceptions - EXCPTNThis test verifies the operation of the MCECC's capability to generate interr

Page 7

Test Descriptions3-60 167Bug Debugging Package UserÕs Manual3Multi-Bit-Error - MBEThis function tests the ECC board's ability to detect multi-bit

Page 8

ECC Memory Board (MCECC) TestsMVME167BUG/D3 3-613Single-Bit-Error - SBEThis function tests the ECC board's ability to correct single-bit-errors.

Page 9

Test Descriptions3-62 167Bug Debugging Package UserÕs Manual3Scrubbing - SCRUBThis function tests refresh "scrubbing" of errors from DRAM.

Page 10 - List of Figures

ECC Memory Board (MCECC) TestsMVME167BUG/D3 3-633Possible first pass scrubbing failure: Timed out waiting for scrubber to start, bd #_ (status __) Tim

Page 11 - List of Tables

Test Descriptions3-64 167Bug Debugging Package UserÕs Manual3MEMC040 Memory Controller (MEMC1/MEMC2) TestsThis section describes the individual MEMC1

Page 12

MEMC040 Memory Controller (MEMC1/MEMC2) TestsMVME167BUG/D3 3-653Alternate Control and Status Registers - ALTC_SThis test checks the Alternate Control

Page 13 - INFORMATION

xi List of Tables Diagnostic Utilities 2-4Diagnostic Test Groups 3-1RAM and SRAM Test Group 3-2RTC Test Group 3-16PCC2 Test Group 3-21MCECC Test Grou

Page 14

Test Descriptions3-66 167Bug Debugging Package UserÕs Manual3Bus Clock Register - BUSCLKThis test checks the Bus Clock Register for proper functionali

Page 15 - Description of 167Bug

MEMC040 Memory Controller (MEMC1/MEMC2) TestsMVME167BUG/D3 3-673Chip ID Register - CHIPIDThis test checks the Chip ID Register for the correct Identif

Page 16 - 167Bug General Information

Test Descriptions3-68 167Bug Debugging Package UserÕs Manual3Chip Revision Register - CHIPREVThis test checks the Chip Revision Register for a valid r

Page 17

MEMC040 Memory Controller (MEMC1/MEMC2) TestsMVME167BUG/D3 3-693RAM Control Register - RAMCNTRLThis test checks the RAM Control Register for proper fu

Page 18

Test Descriptions3-70 167Bug Debugging Package UserÕs Manual3If an interrupt occurs when PAREN and PARINT are off: IRQ occurred while PARINT disabled

Page 19

MEMC040 Memory Controller (MEMC1/MEMC2) TestsMVME167BUG/D3 3-713If during a FAT, a data miscompare error occurs when testing BAD bits: RAM control reg

Page 20 - (Sheet 1 of 3)

Test Descriptions3-72 167Bug Debugging Package UserÕs Manual3MC68040 Internal Cache (DCAC) TestsThis section describes the individual DCAC memory cont

Page 21 - (Sheet 2 of 3)

MC68040 Internal Cache (DCAC) TestsMVME167BUG/D3 3-733Data Cache Copyback - DCAC_CBThis test verifies the basic operation of the MC68040 Data Cache in

Page 22 - (Sheet 3 of 3)

Test Descriptions3-74 167Bug Debugging Package UserÕs Manual3If compare errors are detected when the initial test pattern is verified (in memory) afte

Page 23 - MVME167BUG/D3

MC68040 Internal Cache (DCAC) TestsMVME167BUG/D3 3-753Data Cache Registers - DCAC_RDThis utility provides a display of the MC68040 registers which are

Page 25 - MVME167BUG/D3 1-13

Test Descriptions3-76 167Bug Debugging Package UserÕs Manual3Data Cache Writethrough - DCAC_WTThis test verifies the operation of the MC68040 Data Cac

Page 26 - 166BBug Implementation

MC68040 Internal Cache (DCAC) TestsMVME167BUG/D3 3-773If the test encounters data verify error on data pattern 2, after enabling and disabling data ca

Page 27 - Execute User Program

Test Descriptions3-78 167Bug Debugging Package UserÕs Manual3Serial Port (ST2401) TestsThese sections describe the individual (self) tests of the CD24

Page 28 - Setup System Parameters

Serial Port (ST2401) TestsMVME167BUG/D3 3-793These tests support dual CD2401 devices, even though only one such device is featured on the MVME167. The

Page 29 - Diagnostic Facilities

Test Descriptions3-80 167Bug Debugging Package UserÕs Manual3Baud Rates, Async, Internal Loopback - BAUDThis test verifies that the selected ports wil

Page 30 - Related Documentation

Serial Port (ST2401) TestsMVME167BUG/D3 3-813If all selected ports send and receive the test data successfully, then the test passes: ST2401 BAUD: Bau

Page 31 - Manual Terminology

Test Descriptions3-82 167Bug Debugging Package UserÕs Manual3DMA I/O, Async, Internal Loopback - DMADMA mode refers to a mode where the Direct Memory

Page 32

Serial Port (ST2401) TestsMVME167BUG/D3 3-833If an error occurs while configuring, transmitting, receiving, or reconfiguring, then the test fails: ST2

Page 33 - DIAGNOSTIC FIRMWARE

Test Descriptions3-84 167Bug Debugging Package UserÕs Manual3Polled I/O, Async, Internal Loopback - POLLPolled mode refers to a mode of operation that

Page 34 - Diagnostic Monitor

Serial Port (ST2401) TestsMVME167BUG/D3 3-853If an error occurs during the configuring, data transmission, data reception, or reconfiguring, then the

Page 35 - Command Entry and Directories

MVME167BUG/D3 1-1 1 167BUG GENERALINFORMATION Overview of M68000 Firmware This member of the M68000 firmware family is implemented on the MVME166 and

Page 36 - Utilities

Test Descriptions3-86 167Bug Debugging Package UserÕs Manual3Interrupt I/O, Async, Internal Loopback - INTRInterrupt mode refers to a mode of operatio

Page 37 - MVME167BUG/D3 2-5

Serial Port (ST2401) TestsMVME167BUG/D3 3-873If an error occurs during the configuring, data transmission, data reception, or reconfiguring, then the

Page 38 - Help Extended - Command HEX

Test Descriptions3-88 167Bug Debugging Package UserÕs Manual3ST2401 Error MessagesThe ST2401 test group error messages generally take on the following

Page 39 - Figure 2-1. Help Screen

Memory Management Unit (MMU) TestsMVME167BUG/D3 3-893Memory Management Unit (MMU) TestsThis chapter describes tests to verify basic functionality of t

Page 40 - Loop-On-Error Mode - Prefix LE

Test Descriptions3-90 167Bug Debugging Package UserÕs Manual3Configuration of some parameters that these tests use may be accomplished by the use of t

Page 41 - Non-Verbose Mode - Prefix NV

Memory Management Unit (MMU) TestsMVME167BUG/D3 3-913Display Table Search - DISPSRCHThis utility does a verbose table search operation on the logical

Page 42 - Self Test - Command ST

Test Descriptions3-92 167Bug Debugging Package UserÕs Manual3Build Default Tables - TBLBLDThis utility builds the default translation tables used by t

Page 43 - Zero Pass Count - Command ZP

Memory Management Unit (MMU) TestsMVME167BUG/D3 3-933Verify Default Tables - TBLVERFThis utility verifies the default translation tables used by the M

Page 44 - Diagnostic Firmware

Test Descriptions3-94 167Bug Debugging Package UserÕs Manual3TC Register Test - TCThis test verifies that the page size bit in the Translation Control

Page 45 - TEST DESCRIPTIONS

Memory Management Unit (MMU) TestsMVME167BUG/D3 3-953RP Register Test - RPThis test performs a walking bit test (with complement) on both MC68040 Root

Page 46

167Bug General Information 1-2 167Bug Debugging Package UserÕs Manual1 flow of control for the MVME166 board operating in BootBug mode (166BBug) is s

Page 47 - Memory Addressing - ADR

Test Descriptions3-96 167Bug Debugging Package UserÕs Manual3Tablewalk Mapped Pages - WALKThis test builds and verifies the MMU translation tables for

Page 48 - Alternating Ones/Zeros - ALTS

Memory Management Unit (MMU) TestsMVME167BUG/D3 3-973Mapped ROM Read Test - MAPROMThis test verifies that the MMU can dynamically translate virtual ad

Page 49 - Bit Toggle - BTOG

Test Descriptions3-98 167Bug Debugging Package UserÕs Manual3Used Page Test - USEDPAGEThis test verifies that the USED bits in the table and page desc

Page 50

Memory Management Unit (MMU) TestsMVME167BUG/D3 3-993Modified Page Test - MODPAGEThis test verifies that the MODIFIED bit in the page descriptor for a

Page 51 - Code Execution/Copy - CODE

Test Descriptions3-100 167Bug Debugging Package UserÕs Manual3Invalid Page Test - INVPAGEThis test verifies that if the segment or page descriptor for

Page 52 - Data Patterns - PATS

Memory Management Unit (MMU) TestsMVME167BUG/D3 3-1013Write Protect Page Test - WPPAGEThis test verifies that if the page descriptor for a logical add

Page 53

Test Descriptions3-102 167Bug Debugging Package UserÕs Manual3VME Interface ASIC (VME2) TestsThese sections describe the individual VMEchip2 tests. En

Page 54

VME Interface ASIC (VME2) TestsMVME167BUG/D3 3-1033Register Access - REGAThis test verifies that the registers at offsets 0 through 84 can be read acc

Page 55 - Permutations - PERM

Test Descriptions3-104 167Bug Debugging Package UserÕs Manual3Register Walking Bit - REGBThis test verifies that certain bits in the VMEchip2 ASIC use

Page 56 - Quick Write/Read - QUIK

VME Interface ASIC (VME2) TestsMVME167BUG/D3 3-1053regvrf: bit error: Address ________ Read Data ________ Failin

Page 57 - Memory Refresh Testing - REF

Description of 167Bug MVME167BUG/D3 1-31 Figure 1-1. Flow Diagram of Board Operational Mode (Sheet 1 of 4) NOTE: This diagram applies to the 1

Page 58

Test Descriptions3-106 167Bug Debugging Package UserÕs Manual3Software Interrupts (Polled Mode) - SWIAThis test verifies that all software interrupts

Page 59 - Random Data - RNDM

VME Interface ASIC (VME2) TestsMVME167BUG/D3 3-1073After the interrupt is generated, the clear bit for the current SWI interrupter is asserted and a c

Page 60 - MK48T0x (RTC) Tests

Test Descriptions3-108 167Bug Debugging Package UserÕs Manual3Software Interrupts (Processor Interrupt Mode) - SWIBThis test verifies that all softwar

Page 61 - BBRAM Addressing - ADR

VME Interface ASIC (VME2) TestsMVME167BUG/D3 3-1093If the received interrupt vector is not that of the programmed interrupt vector: Unexpected Vector

Page 62 - Clock Function - CLK

Test Descriptions3-110 167Bug Debugging Package UserÕs Manual3Software Interrupts Priority - SWICThis test verifies that all software interrupts (1 th

Page 63 - Data Miscompare Error:

VME Interface ASIC (VME2) TestsMVME167BUG/D3 3-1113If the programmed interrupt did not occur: Software Interrupt did not occur Status: Expected =_____

Page 64 - Battery Backed-Up SRAM - RAM

Test Descriptions3-112 167Bug Debugging Package UserÕs Manual3Timer Accuracy Test - TACUThis test performs a four point verification of the VMEChip2 A

Page 65

VME Interface ASIC (VME2) TestsMVME167BUG/D3 3-1133If the prescaler calibration register does not contain one of four legal MPU clock calibration valu

Page 66 - Prescaler Clock Adjust - ADJ

Test Descriptions3-114 167Bug Debugging Package UserÕs Manual3Tick Timer Increment - TMRA, TMRBThis test verifies that Timer x Counter Register (x = 1

Page 67 - FAST Bit - FAST

VME Interface ASIC (VME2) TestsMVME167BUG/D3 3-1153Prescaler Clock Adjust - TMRCThis test proves that the Prescaler Clock Adjust register can vary the

Page 68 - GPIO Interrupts - GPIO

167Bug General Information 1-4 167Bug Debugging Package UserÕs Manual1 Figure 1-1. Flow Diagram of Board Operational Mode (Sheet 2 of 4) NOTE: This

Page 69

Test Descriptions3-116 167Bug Debugging Package UserÕs Manual3Tick Timer No Clear On Compare - TMRD, TMREThis test verifies the Tick Timers No Clear O

Page 70 - LANC Interrupts - LANC

VME Interface ASIC (VME2) TestsMVME167BUG/D3 3-1173Tick Timer Clear On Compare - TMRF, TMRGThis test verifies the Tick Timers Clear On Compare mode. T

Page 71

Test Descriptions3-118 167Bug Debugging Package UserÕs Manual3Overflow Counter - TMRH, TMRIThis test enables the overflow counter and a count of timer

Page 72 - MIEN Bit - MIEN

VME Interface ASIC (VME2) TestsMVME167BUG/D3 3-1193Watchdog Timer Counter - TMRJThe watchdog timer is tested to ensure functionality at all programmab

Page 73 - Prescaler Clock - PCLK

Test Descriptions3-120 167Bug Debugging Package UserÕs Manual3Watchdog Timer Board Fail - TMRKThe watchdog timer is tested in board fail mode by setti

Page 74

VSB Interface ASIC (VSB2) TestsMVME167BUG/D3 3-1213VSB Interface ASIC (VSB2) TestsThese sections describe the individual VSBchip2 tests for the MVME16

Page 75

Test Descriptions3-122 167Bug Debugging Package UserÕs Manual3Register Access - REGACCThis test verifies that the registers within the VSBchip2 are ac

Page 76

VSB Interface ASIC (VSB2) TestsMVME167BUG/D3 3-1233Local Walking Bit - L_WKBThis test verifies that the bits of the VSBchip2 registers can be individu

Page 77

Test Descriptions3-124 167Bug Debugging Package UserÕs Manual3If the test fails due to a bit not being properly set/cleared: VSB2 L_WKB: Local Wal

Page 78

VSB Interface ASIC (VSB2) TestsMVME167BUG/D3 3-1253Prescaler Count Register - PRSCALThis test verifies the operation and accuracy of the VSBchip2&apos

Page 79

Description of 167Bug MVME167BUG/D3 1-51 Figure 1-1. Flow Diagram of Board Operational Mode (Sheet 3 of 4) NOTE: This diagram applies to the 167Bug

Page 80

Test Descriptions3-126 167Bug Debugging Package UserÕs Manual3If the test fails the accuracy test (prescale count register value was not within expect

Page 81

VSB Interface ASIC (VSB2) TestsMVME167BUG/D3 3-1273Local Write Post Interrupt - L_WP_WIThis diagnostic verifies the capability of the VSBchip2 to gene

Page 82

Test Descriptions3-128 167Bug Debugging Package UserÕs Manual3If the local write post error interrupt is never generated: VSB2 L_WP_WI: Local Writ

Page 83

MC68230 Parallel Interface/Timer (PIT) TestsMVME167BUG/D3 3-1293MC68230 Parallel Interface/Timer (PIT) TestsThese sections describe the individual (se

Page 84 - Device Access - REGA

Test Descriptions3-130 167Bug Debugging Package UserÕs Manual3PI/T Port's Register/Data - REGThis test simply writes and then reads all possible

Page 85 - Register Access - REGB

MC68230 Parallel Interface/Timer (PIT) TestsMVME167BUG/D3 3-1313PI/T Port's IRQ - IRQThis test will exercise the interrupt capabilities of the MC

Page 86 - Timer 1 Counter - TMR1A

Test Descriptions3-132 167Bug Debugging Package UserÕs Manual3If the PI/T port status register contains the wrong value: PIT IRQ: PI/T Port'

Page 87 - Timer 1 Free-Run - TMR1B

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1333LAN Coprocessor for Ethernet (LANC) TestsThis section describes the individual Local Area

Page 88

Test Descriptions3-134 167Bug Debugging Package UserÕs Manual3The individual tests are described in alphabetical order on the following pages. The err

Page 89

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1353Chip Self Test - CSTThis test verifies that the 82596 self-test mode (command) can be exe

Page 90 - Timer 1 Interrupts - TMR1E

167Bug General Information 1-6 167Bug Debugging Package UserÕs Manual1 Figure 1-1. Flow Diagram of Board Operational Mode (Sheet 4 of 4) NOTE: This

Page 91

Test Descriptions3-136 167Bug Debugging Package UserÕs Manual3If any failures occur, the following is displayed (more descriptive text then follows):

Page 92 - Timer 2 Counter - TMR2A

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1373Diagnose Internal Hardware - DIAGThis test verifies that the Diagnose command of the 8259

Page 93 - Timer 2 Free-Run - TMR2B

Test Descriptions3-138 167Bug Debugging Package UserÕs Manual3Phase 2: 1. Resets Exponential Backoff Shift Register and all counters. 2. Temporarily c

Page 94

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1393Dump Configuration/Registers - DUMPThis test verifies that the Dump command of the 82596 c

Page 95

Test Descriptions3-140 167Bug Debugging Package UserÕs Manual3External Loopback Cable - ELBCThe 82596 has three modes of loopback: Internal Loopback,

Page 96 - Timer 2 Interrupts - TMR2E

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1413Once the data packet has been set up to be transmitted, the test instructs the 82596 (thr

Page 97

Test Descriptions3-142 167Bug Debugging Package UserÕs Manual3Once the transmitted data has been received, the test verifies the status of the receive

Page 98 - Vector Base Register - VBR

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1433External Loopback Transceiver - ELBTThe 82596 has three modes of loopback: Internal Loopb

Page 99

Test Descriptions3-144 167Bug Debugging Package UserÕs Manual3The status bits of the error message display indicate the source of the problem: TRANSMI

Page 100

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1453Once the transmitted data has been received, the test verifies the status of the receive

Page 101 - Check-Bit DRAM - CBIT

Description of 167Bug MVME167BUG/D3 1-71 Figure 1-2. Flow Diagram of 166Bug/167Bug System Operational Mode SYSTEM10915.00 9402ERRORERRORNO ERRORSWAI

Page 102 - The test ends with:

Test Descriptions3-146 167Bug Debugging Package UserÕs Manual3+12VDC Fuse - FUSEThis test verifies that the +12VDC Fuse indicator (via the VMEChip2) i

Page 103 - Exceptions - EXCPTN

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1473Internal Loopback - ILBThe 82596 has three modes of loopback: Internal Loopback, External

Page 104 - Multi-Bit-Error - MBE

Test Descriptions3-148 167Bug Debugging Package UserÕs Manual3The status bits of the error message display indicate the source of the problem: TRANSMI

Page 105 - Single-Bit-Error - SBE

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1493Once the transmitted data has been received, the test verifies the status of the receive

Page 106 - Scrubbing - SCRUB

Test Descriptions3-150 167Bug Debugging Package UserÕs Manual3Interrupt Request - IRQThis test verifies that the 82596 can assert an interrupt request

Page 107

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1513Monitor (Incoming Frames) Mode - MONThis test is subclassed as a utility test. This utili

Page 108

Test Descriptions3-152 167Bug Debugging Package UserÕs Manual3Time Domain Reflectometry - TDRThis test verifies that Time Domain Reflectometry (TDR) ca

Page 109

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1533Command Input: 167-Diag>LANC TDR Response/Messages: After the command has been issued,

Page 110 - Bus Clock Register - BUSCLK

Test Descriptions3-154 167Bug Debugging Package UserÕs Manual3Additional Error MessagesThe following error messages, and descriptions for each, may ap

Page 111 - Chip ID Register - CHIPID

LAN Coprocessor for Ethernet (LANC) TestsMVME167BUG/D3 3-1553At the completion of each test in the LANC test group the LANC error status register (PCC

Page 112

Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omiss

Page 113

167Bug General Information 1-8 167Bug Debugging Package UserÕs Manual1 Figure 1-3. Flow Diagram of 166BootBug Board Operational Mode (Sheet 1 of 3)

Page 114

Test Descriptions3-156 167Bug Debugging Package UserÕs Manual3command execution function waits for one second for the 82596 to post the completion of

Page 115 - MVME167BUG/D3 3-71

NCR 53C710 SCSI I/O Processor (NCR) TestsMVME167BUG/D3 3-1573NCR 53C710 SCSI I/O Processor (NCR) TestsThese sections describe the individual NCR 53C71

Page 116

Test Descriptions3-158 167Bug Debugging Package UserÕs Manual3Device Access - ACC1This procedure tests the basic ability to access the NCR 53C710 devi

Page 117 - Data Cache Copyback - DCAC_CB

NCR 53C710 SCSI I/O Processor (NCR) TestsMVME167BUG/D3 3-1593Unsolicited Exception: Program Counter ________ Vector Number ___

Page 118

Test Descriptions3-160 167Bug Debugging Package UserÕs Manual3Register Access - ACC2This procedure tests the basic ability to access the NCR 53C710 re

Page 119

NCR 53C710 SCSI I/O Processor (NCR) TestsMVME167BUG/D3 3-1613TEMP Register Error: Address =________, Expected =________, Actual =________ DMA Next Add

Page 120

Test Descriptions3-162 167Bug Debugging Package UserÕs Manual3DMA FIFO - DFIFOThis procedure tests the basic ability to write data into the DMA FIFO a

Page 121

NCR 53C710 SCSI I/O Processor (NCR) TestsMVME167BUG/D3 3-1633Interrupts - IRQThis test verifies that level 0 interrupts will not generate an interrupt

Page 122 - Serial Port (ST2401) Tests

Test Descriptions3-164 167Bug Debugging Package UserÕs Manual3Interrupt Control "IEN" bit not set Address =________, Expected =__, Actual =_

Page 123 - MVME167BUG/D3 3-79

NCR 53C710 SCSI I/O Processor (NCR) TestsMVME167BUG/D3 3-1653Unsolicited Exception: Program Counter ________ Vector Number ___

Page 124

Description of 167Bug MVME167BUG/D3 1-91 Figure 1-3. Flow Diagram of 166BootBug Board Operational Mode (Sheet 2 of 3)SET UP DEBUGGER VARIABLESGO TO

Page 125 - MVME167BUG/D3 3-81

Test Descriptions3-166 167Bug Debugging Package UserÕs Manual3Loopback - LPBKThe 53C710 Loopback Mode in effect, lets the chip talk to itself. When th

Page 126 - 167-Diag>ST2401 DMA

NCR 53C710 SCSI I/O Processor (NCR) TestsMVME167BUG/D3 3-1673SCRIPTs Processor - SCRIPTSThis test initializes the test structures and makes use of the

Page 127 - MVME167BUG/D3 3-83

Test Descriptions3-168 167Bug Debugging Package UserÕs Manual3Command Input: 167-Diag>NCR SCRIPTSResponse/Messages: After the command has been issu

Page 128

NCR 53C710 SCSI I/O Processor (NCR) TestsMVME167BUG/D3 3-1693Interrupt Status "DIP" bit not set Address =________, Expected =__, Actual =__

Page 129 - MVME167BUG/D3 3-85

Test Descriptions3-170 167Bug Debugging Package UserÕs Manual3SCSI FIFO - SFIFOThis procedure tests the basic ability to write data into the SCSI FIFO

Page 130 - 167-Diag>ST2401 INTR

MVME167BUG/D34-14MVME167BUGENVIRONMENTIntroductionCertain parameters contained in the MVME167's Non-Volatile RAM (NVRAM), also known as Battery B

Page 131 - MVME167BUG/D3 3-87

MVME167Bug Environment4-2 167Bug Debugging Package UserÕs Manual4Manual for the actual location and other information about the board information bloc

Page 132 - ST2401 Error Messages

Set Environment to Bug/Operating System (ENV)MVME167BUG/D3 4-34B Use both the GCSR and the MPCR methods to pass and start execution of cross-loaded pr

Page 133

MVME167Bug Environment4-4 167Bug Debugging Package UserÕs Manual4Auto Boot Device LUN = 00? Refer to Appendix E in the Debugging Package for Motor

Page 134

Set Environment to Bug/Operating System (ENV)MVME167BUG/D3 4-54ROM Boot Direct Ending Address = FFBFFFFC? This is the last location tested when the

Page 135

167Bug General Information 1-10 167Bug Debugging Package UserÕs Manual1 Figure 1-3. Flow Diagram of 166BootBug Board Operational Mode(Sheet 3 of 3)D

Page 136 - Build Default Tables - TBLBLD

MVME167Bug Environment4-6 167Bug Debugging Package UserÕs Manual4simultaneously. The default Memory Search Starting Address is$00000000. Memory Search

Page 137 - 167-Diag>MMU TBLVERF

Set Environment to Bug/Operating System (ENV)MVME167BUG/D3 4-74Memory Size Enable [Y/N] = Y? Y Memory will be sized for Self Test diagnostics.

Page 138 - TC Register Test - TC

MVME167Bug Environment4-8 167Bug Debugging Package UserÕs Manual4Slave Ending Address #1 = 01FFFFFF? This is the ending address of the local resourc

Page 139 - RP Register Test - RP

Set Environment to Bug/Operating System (ENV)MVME167BUG/D3 4-94This register deÞnes which bits of the address are signiÞcant. A logical oneÒ1Ó indicat

Page 140 - Tablewalk Mapped Pages - WALK

MVME167Bug Environment4-10 167Bug Debugging Package UserÕs Manual4Master Control #2 = 00? This deÞnes the access characteristics for the address space

Page 141 - Mapped ROM Read Test - MAPROM

Set Environment to Bug/Operating System (ENV)MVME167BUG/D3 4-114Master Address Translation Address #4 = 00000000? This register will allow the VMEbus

Page 142 - Used Page Test - USEDPAGE

MVME167Bug Environment4-12 167Bug Debugging Package UserÕs Manual4PCC2 Vector Base = 05? VMEC2 Vector Base #1 = 06? VMEC2 Vector

Page 143 - Modified Page Test - MODPAGE

Set Environment to Bug/Operating System (ENV)MVME167BUG/D3 4-134Configure MVME166Bug ParametersThe additional parameters that can be configured using E

Page 144 - Invalid Page Test - INVPAGE

MVME167Bug Environment4-14 167Bug Debugging Package UserÕs Manual4VSBC2 Slave Ending Address #1 = 00000000? This is the ending address of an addre

Page 145

Set Environment to Bug/Operating System (ENV)MVME167BUG/D3 4-154VSBC2 Requester Control = 01000000? The bits in this register control aspect

Page 146

167Bug Implementation MVME167BUG/D3 1-111 167Bug Implementation Physically, 167Bug is contained in two of the four 44-pin PLCC/CLCC EPROMs, providing

Page 147 - Register Access - REGA

MVME167Bug Environment4-16 167Bug Debugging Package UserÕs Manual4VSBC2 Master Ending Address #2 = 00000000? This is the ending address of an addres

Page 148 - Register Walking Bit - REGB

Set Environment to Bug/Operating System (ENV)MVME167BUG/D3 4-174VSBC2 Master Ending Address #4 = 00000000? This is the ending address of an address

Page 149 - VME2/REGB Test Failure Data:

MVME167Bug Environment4-18 167Bug Debugging Package UserÕs Manual4

Page 150

IN-19IndexSymbols+12VDC Fuse (FUSE) 3-146Numerics166BBug Implementation 1-14166Buggeneral information 1-1implementation 1-11167Buggeneral information

Page 151 - MVME167BUG/D3 3-107

IndexIN-20INDEXChip Self Test (CST) 3-135CHIPID 3-67CHIPREV 3-68Clear (Zero) Error Counters - CommandZE 2-10Clear Error Messages - Command CEM2-5Clear

Page 152

IN-21INDEXEECC Memory Board (MCECC) Tests 3-55EIA-232-D port 1-13ELBC 3-140ELBT 3-143ENV 4-1, 4-2environmental parameters 4-1EPROMs 1-11, 1-13error co

Page 153

IndexIN-22INDEXLL_PRSCAL 3-125L_WKB 3-123L_WP_WI 3-127LA 2-8LAN Coprocessor for Ethernet (LANC)Tests 3-133LANC 3-26LANC Error Messages 3-154LANC Inter

Page 154

IN-23INDEXOOverflow Counter 3-45, 3-51Overflow Counter - TMRH, TMR 3-118overview of diagnostic firmware 2-1overview of M68000 firmware 1-1Ppage test 3

Page 155

IndexIN-24INDEXSCSI I/O Processor Tests 3-157SCSI specification 1-19SD 2-10SD Command 1-1, 1-17SE 2-10SEL Interrupts 3-34Self Test - Command ST 2-10Se

Page 156 - Timer Accuracy Test - TACU

IN-25INDEXTMRH, TMRI 3-118TMRJ 3-119TMRK 3-120toggle bits 3-5Translation Control register 3-94TRXC4 1-13UUsed Page Test - USEDPAGE 3-98USEDPAGE 3-98ut

Page 157

167Bug General Information 1-12 167Bug Debugging Package UserÕs Manual1 The default condition is with all eight jumpers installed, between pins 1-2,

Page 158

Detailed Installation and Start-Up MVME167BUG/D3 1-1313. On the MVME167 only, install jumpers on headers J6 and J7 to conÞgure serial port 4 to use c

Page 159 - Prescaler Clock Adjust - TMRC

167Bug General Information1-14 167Bug Debugging Package UserÕs Manual1BOOTBUG166BBug ImplementationThe MVME166 board has a byte-wide EPROM in addition

Page 160

BOOTBUGMVME167BUG/D3 1-151There is a jumper on the MVME166 board that controls the operation of the BootBug. If the jumper at J3 pins 7 and 8 is in p

Page 161

167Bug General Information1-16 167Bug Debugging Package UserÕs Manual1Setup System ParametersSETUP Setup allows configuring certain parameters that ar

Page 162 - Overflow Counter - TMRH, TMRI

ROMbootMVME167BUG/D3 1-171ROMbootThere are two spare EPROM sockets, XU3 and XU4, available to carry user-programmed EPROMs. Therefore, you do not hav

Page 163 - Watchdog Timer Counter - TMRJ

Preface The MVME167Bug Debugging Package UserÕs Manual provides general information and a diagnostic Þrmware guide for the MVME167Bug (167Bug) Debu

Page 164

167Bug General Information1-18 167Bug Debugging Package UserÕs Manual1Related DocumentationThe following publications are applicable to 167Bug and may

Page 165

Manual TerminologyMVME167BUG/D3 1-191Versatile Backplane Bus: VMEbus, ANSI/IEEE Std 1014-1987, The Institute of Electrical and Electronics Engineers,

Page 166 - Register Access - REGACC

167Bug General Information1-20 167Bug Debugging Package UserÕs Manual1

Page 167 - Local Walking Bit - L_WKB

MVME167BUG/D32-12DIAGNOSTIC FIRMWAREScopeThis chapter contains information about the operation and use of the MVME167 Diagnostic Firmware Package, her

Page 168

Diagnostic Firmware2-2 167Bug Debugging Package UserÕs Manual2CompatibilityAlthough the MVME167 diagnostic package contains a totally new test set, th

Page 169

Diagnostic MonitorMVME167BUG/D3 2-32Command Entry and DirectoriesEntry of commands is made when the prompt 167-Diag> appears. The mnemonic name for

Page 170

Diagnostic Firmware2-4 167Bug Debugging Package UserÕs Manual2UtilitiesIn addition to individual or sets of tests, the diagnostic package supports the

Page 171

UtilitiesMVME167BUG/D3 2-52Append Error Messages Mode - Command AEMThis command allows you to accumulate error messages in the internal error message

Page 172

Diagnostic Firmware2-6 167Bug Debugging Package UserÕs Manual2Display Error Messages - Command DEMThis command allows you to display (dump) the intern

Page 173 - IRQ Interrupt test

UtilitiesMVME167BUG/D3 2-72 Figure 2-1. Help Screen167-Diag>he AEMAppend Error Messages Mode CEMClear Error Messages CFConfiguration Editor DCACM

Page 174

The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., Þrst published 1990, and may be us

Page 175 - PI/T Port's IRQ - IRQ

Diagnostic Firmware2-8 167Bug Debugging Package UserÕs Manual2Loop Always Mode - Prefix LATo endlessly repeat a test or series of tests, the prefix LA

Page 176

UtilitiesMVME167BUG/D3 2-92Loop Non-Verbose Mode - Prefix LNThe LN command modifies the way that a failed test is endlessly repeated. The LN command ha

Page 177

Diagnostic Firmware2-10 167Bug Debugging Package UserÕs Manual2Switch Directories - Command SDTo leave the diagnostic directory (and disable the diagn

Page 178 - 167-Diag>CF LANC

UtilitiesMVME167BUG/D3 2-112Zero Pass Count - Command ZPInvoking the ZP command resets the pass counter to zero. This is frequently desirable before t

Page 179 - Chip Self Test - CST

Diagnostic Firmware2-12 167Bug Debugging Package UserÕs Manual2

Page 180 - (error message)

MVME167BUG/D33-13TEST DESCRIPTIONSDetailed descriptions of 167Bug's diagnostic tests are presented in this chapter. The test sets are described

Page 181 - MVME167BUG/D3 3-137

Test Descriptions3-2 167Bug Debugging Package UserÕs Manual3Local RAM (RAM) and Static RAM (SRAM) TestsThese sections describe the individual RAM and

Page 182

Local RAM (RAM) and Static RAM (SRAM) TestsMVME167BUG/D3 3-33Memory Addressing - ADRThis is the memory addressability test, the purpose of which is to

Page 183

Test Descriptions3-4 167Bug Debugging Package UserÕs Manual3Alternating Ones/Zeros - ALTSThis test verifies addressing of memory in the range specifie

Page 184

Local RAM (RAM) and Static RAM (SRAM) TestsMVME167BUG/D3 3-53Bit Toggle - BTOGThe memory range is specified by the RAM test directory configuration pa

Page 185 - RECEIVE Data Time-Out

Contents Overview of M68000 Firmware 1-1Description of 167Bug 1-1167Bug Implementation 1-11166Bug Implementation 1-11Detailed Installation and Start-

Page 186

Test Descriptions3-6 167Bug Debugging Package UserÕs Manual3If the test fails, then the display appears as follows. RAM BTOG: Bit Toggle...

Page 187

Local RAM (RAM) and Static RAM (SRAM) TestsMVME167BUG/D3 3-73Code Execution/Copy - CODECopy test code to memory and execute. The code in the memory u

Page 188

Test Descriptions3-8 167Bug Debugging Package UserÕs Manual3Data Patterns - PATSIf the test address range (test range) is less than 8 bytes, the test

Page 189

Local RAM (RAM) and Static RAM (SRAM) TestsMVME167BUG/D3 3-93Local Parity Memory Error Detection - PEDThe memory range and address increment is specif

Page 190 - +12VDC Fuse - FUSE

Test Descriptions3-10 167Bug Debugging Package UserÕs Manual3If an unexpected exception, such as a parity error being detected as the parity bit was b

Page 191 - Internal Loopback - ILB

Local RAM (RAM) and Static RAM (SRAM) TestsMVME167BUG/D3 3-113Permutations - PERMThis command performs a test which verifies that the memory in the t

Page 192

Test Descriptions3-12 167Bug Debugging Package UserÕs Manual3Quick Write/Read - QUIKEach pass of this test fills the test range with a data pattern by

Page 193

Local RAM (RAM) and Static RAM (SRAM) TestsMVME167BUG/D3 3-133Memory Refresh Testing - REFThe memory range and address increment is specified by the R

Page 194 - Interrupt Request - IRQ

Test Descriptions3-14 167Bug Debugging Package UserÕs Manual3or: RAM/REF Test Failure Data: RTC is in read mode, invoke SET command. If a data verifi

Page 195 - 167-Diag>LANC MON

Local RAM (RAM) and Static RAM (SRAM) TestsMVME167BUG/D3 3-153Random Data - RNDMThe test block is the memory range specified by the RAM test group con

Page 196

Loop-On-Error Mode - PreÞx LE 2-8Line Feed Suppression Mode - PreÞx LF 2-8Loop Non-Verbose Mode - PreÞx LN 2-9Display/Revise Self Test Mask - Command

Page 197

Test Descriptions3-16 167Bug Debugging Package UserÕs Manual3MK48T0x (RTC) TestsThese tests check the BBRAM, SRAM, and clock portions of the MK48T08 R

Page 198 - Additional Error Messages

MK48T0x (RTC) TestsMVME167BUG/D3 3-173BBRAM Addressing - ADRThis test is designed to assure proper addressability of the MK48T0x BBRAM. The algorithm

Page 199

Test Descriptions3-18 167Bug Debugging Package UserÕs Manual3Clock Function - CLKThis test verifies the functionality of the Real Time Clock (RTC). T

Page 200

MK48T0x (RTC) TestsMVME167BUG/D3 3-193If the predetermined number of reads are made before the seconds register changed, the following message is prin

Page 201

Test Descriptions3-20 167Bug Debugging Package UserÕs Manual3Battery Backed-Up SRAM - RAMThis test performs a data test on each SRAM location of the M

Page 202 - Device Access - ACC1

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-213Peripheral Channel Controller (PCC2) TestsThese sections describe the individual PCCchip2

Page 203

Test Descriptions3-22 167Bug Debugging Package UserÕs Manual3Prescaler Clock Adjust - ADJVerifies that the Prescaler Clock Adjust Register can vary th

Page 204 - Register Access - ACC2

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-233FAST Bit - FASTVerifies the FAST/SLOW access time to BBRAM by using Tick Timer 1 to measu

Page 205

Test Descriptions3-24 167Bug Debugging Package UserÕs Manual3GPIO Interrupts - GPIOVerifies that level 0 interrupts will not generate an interrupt, bu

Page 206 - DMA FIFO - DFIFO

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-253Interrupt did not occur Status: Expected =__, Actual =__ Vector: Expected =__, Actual =__

Page 207 - Interrupts - IRQ

Timer 1 Clear On Compare - TMR1C 3-44Timer 1 Overßow Counter - TMR1D 3-45Timer 1 Interrupts - TMR1E 3-46Timer 2 Counter - TMR2A 3-48Timer 2 Free-Run

Page 208

Test Descriptions3-26 167Bug Debugging Package UserÕs Manual3LANC Interrupts - LANCVerifies that level 0 interrupts will not generate an interrupt, bu

Page 209

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-273Interrupt did not occur Status: Expected =__, Actual =__ Vector: Expected =__, Actual =__

Page 210 - Loopback - LPBK

Test Descriptions3-28 167Bug Debugging Package UserÕs Manual3MIEN Bit - MIENUses the General Purpose I/O Interrupt Control to generate and service a l

Page 211 - SCRIPTs Processor - SCRIPTS

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-293Prescaler Clock - PCLKVerifies the accuracy of the Prescaler Clock, by using a constant t

Page 212

Test Descriptions3-30 167Bug Debugging Package UserÕs Manual3Printer `ACK' Interrupts - PRNTAVerifies that level 0 interrupts will not generate a

Page 213

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-313Interrupt did not occur Status: Expected =__, Actual =__Vector: Expected =__, Actual =__

Page 214 - SCSI FIFO - SFIFO

Test Descriptions3-32 167Bug Debugging Package UserÕs Manual3Printer `FAULT' Interrupts - PRNTBVerifies that level 0 interrupts will not generate

Page 215 - ENVIRONMENT

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-333Interrupt did not occur Status: Expected =__, Actual =__ Vector: Expected =__, Actual =__

Page 216

Test Descriptions3-34 167Bug Debugging Package UserÕs Manual3Printer `SEL' Interrupts - PRNTCVerifies that level 0 interrupts will not generate a

Page 217

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-353Interrupt did not occur Status: Expected =__, Actual =__ Vector: Expected =__, Actual =__

Page 218

Invalid Page Test - INVPAGE 3-100Write Protect Page Test - WPPAGE 3-101VME Interface ASIC (VME2) Tests 3-102Register Access - REGA 3-103Register Walk

Page 219

Test Descriptions3-36 167Bug Debugging Package UserÕs Manual3Printer `PE' Interrupts - PRNTDVerifies that level 0 interrupts will not generate an

Page 220

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-373Interrupt did not occurStatus: Expected =__, Actual =__ Vector: Expected =__, Actual =__

Page 221 - Configure VMEbus Interface

Test Descriptions3-38 167Bug Debugging Package UserÕs Manual3Printer `BUSY' Interrupts - PRNTEVerifies that level 0 interrupts will not generate

Page 222

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-393Interrupt did not occur Status: Expected =__, Actual =__ Vector: Expected =__, Actual =__

Page 223

Test Descriptions3-40 167Bug Debugging Package UserÕs Manual3Device Access - REGAAll the device registers (except the "PIACK" registers) are

Page 224

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-413Register Access - REGBThe device data lines are checked by successive writes and reads to

Page 225

Test Descriptions3-42 167Bug Debugging Package UserÕs Manual3Timer 1 Counter - TMR1AVerifies the Tick Timer Counter Register write/read ability and fu

Page 226

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-433Timer 1 Free-Run - TMR1BVerifies the Compare Register write/read ability and the function

Page 227

Test Descriptions3-44 167Bug Debugging Package UserÕs Manual3Timer 1 Clear On Compare - TMR1CVerifies the Clear On Compare functionality by setting th

Page 228

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-453Timer 1 Overflow Counter - TMR1DVerifies the Overflow Counter functionality by performing

Page 229

Loopback - LPBK 3-166SCRIPTs Processor - SCRIPTS 3-167SCSI FIFO - SFIFO 3-170Introduction 4-1ConÞgure Board Information Block (CNFG) 4-1Set Environme

Page 230

Test Descriptions3-46 167Bug Debugging Package UserÕs Manual3Timer 1 Interrupts - TMR1EVerifies that level 0 interrupts will not generate an interrupt

Page 231 - MVME167BUG/D3 4-17

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-473Interrupt did not occur Status: Expected =__, Actual =__ Vector: Expected =__, Actual =__

Page 232 - MVME167Bug Environment

Test Descriptions3-48 167Bug Debugging Package UserÕs Manual3Timer 2 Counter - TMR2AVerifies the Tick Timer Counter Register write/read ability and fu

Page 233 - Numerics

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-493Timer 2 Free-Run - TMR2BVerifies the Compare Register write/read ability and the function

Page 234

Test Descriptions3-50 167Bug Debugging Package UserÕs Manual3Timer 2 Clear On Compare - TMR2CVerifies the Clear On Compare functionality by setting th

Page 235

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-513Timer 2 Overflow Counter - TMR2DVerifies the Overflow Counter functionality by performing

Page 236

Test Descriptions3-52 167Bug Debugging Package UserÕs Manual3Timer 2 Interrupts - TMR2EVerifies that level 0 interrupts will not generate an interrupt

Page 237

Peripheral Channel Controller (PCC2) TestsMVME167BUG/D3 3-533Interrupt did not occurStatus: Expected =__, Actual =__ Vector: Expected =__, Actual =__S

Page 238

Test Descriptions3-54 167Bug Debugging Package UserÕs Manual3Vector Base Register - VBRUses the General Purpose I/O Interrupt Control to generate and

Page 239

ECC Memory Board (MCECC) TestsMVME167BUG/D3 3-553ECC Memory Board (MCECC) TestsThis section describes the individual MCECC memory tests. Entering MCE

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