Motorola MCU MC9S12DP256 Manuel d'utilisateur

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PIM_9DP256 Block User Guide V02.07101.3 Block DiagramFigure 1-1 is a block diagram of the PIM_9DP256.Figure 1-1 PIM_9DP256 Block DiagramPort TPT0PT1

PIM_9DP256 Block User Guide V02.0711Section 2 External Signal Description2.1 OverviewThis section lists and describes the signals that do connect o

PIM_9DP256 Block User Guide V02.0712Port MPM7TXCAN3 MSCAN3 transmit pinGPIOTXCAN4 MSCAN4 transmit pinGPIO General-purpose I/OPM6RXCAN3 MSCAN3 receive

PIM_9DP256 Block User Guide V02.0713Port PPP7PWM7 Pulse Width Modulator channel 7GPIOSCK2 Serial Peripheral Interface 2 serial clock pinGPIO/KWP7 Gen

PIM_9DP256 Block User Guide V02.0714Port HPH7SS2Serial Peripheral Interface 2 slave select output in master mode,input for slave mode or master mode.G

PIM_9DP256 Block User Guide V02.0715Port EPE7NOACC/XCLKS/GPIORefer to MEBI in HCS12 Core User Guide.PE6IPIPE1/MODB/GPIOPE5IPIPE0/MODA/GPIOPE4 ECLK/GP

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PIM_9DP256 Block User Guide V02.0717Section 3 Memory Map and Registers3.1 OverviewThis section provides a detailed description of all registers.3.2

PIM_9DP256 Block User Guide V02.0718NOTE:Register Address = Base Address + Address Offset, where the Base Address isdefined at the MCU level and the A

PIM_9DP256 Block User Guide V02.0719Table 3-2 Pin Configuration SummaryNOTE:All bits of all registers in this module are completely synchronous to i

PIM_9DP256 Block User Guide V02.072Revision HistoryVersionNumberRevisionDateEffectiveDateAuthor Description of ChangesV02.0019 FEB2001Initial version

PIM_9DP256 Block User Guide V02.0720If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,

PIM_9DP256 Block User Guide V02.0721Figure 3-4 Port T Reduced Drive Register (RDRT)Read:Anytime.Write:Anytime.This register configures the drive str

PIM_9DP256 Block User Guide V02.0722Figure 3-6 Port T Polarity Select Register (PPST)Read:Anytime.Write:Anytime.This register selects whether a pull-

PIM_9DP256 Block User Guide V02.0723Figure 3-8 Port S Input Register (PTIS)Read:Anytime.Write:Never, writes to this register have no effect.This reg

PIM_9DP256 Block User Guide V02.0724Figure 3-10 Port S Reduced Drive Register (RDRS)Read:Anytime.Write:Anytime.This register configures the drive str

PIM_9DP256 Block User Guide V02.0725Figure 3-12 Port S Polarity Select Register (PPSS)Read:Anytime.Write:Anytime.This register selects whether a pul

PIM_9DP256 Block User Guide V02.07263.3.3 Port M RegistersFigure 3-14 Port M I/O Register (PTM)Read:Anytime.Write:Anytime.If the data direction bits

PIM_9DP256 Block User Guide V02.0727Figure 3-16 Port M Data Direction Register (DDRM)Read:Anytime.Write:Anytime.This register configures each port M

PIM_9DP256 Block User Guide V02.0728Figure 3-18 Port M Pull Device Enable Register (PERM)Read:Anytime.Write:Anytime.This register configures whether

PIM_9DP256 Block User Guide V02.0729Figure 3-20 Port M Wired-Or Mode Register (WOMM)Read:Anytime.Write:Anytime.This register configures the output p

PIM_9DP256 Block User Guide V02.073Table of ContentsSection 1 Introduction1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIM_9DP256 Block User Guide V02.0730MODRR[3:2] — CAN4 RoutingMODRR[4] — SPI0 RoutingMODRR[5] — SPI1 RoutingMODRR[6] — SPI2 RoutingNOTES:1. Routing to

PIM_9DP256 Block User Guide V02.07313.3.4 Port P RegistersFigure 3-22 Port P I/O Register (PTP)Read:Anytime.Write:Anytime.If the data direction bit

PIM_9DP256 Block User Guide V02.0732Figure 3-24 Port P Data Direction Register (DDRP)Read:Anytime.Write:Anytime.This register configures each port P

PIM_9DP256 Block User Guide V02.07330 = Full drive strength at output.Figure 3-26 Port P Pull Device Enable Register (PERP)Read:Anytime.Write:Anytim

PIM_9DP256 Block User Guide V02.0734Figure 3-28 Port P Interrupt Enable Register (PIEP)Read:Anytime.Write:Anytime.This register disables or enables o

PIM_9DP256 Block User Guide V02.07353.3.5 Port H RegistersFigure 3-30 Port H I/O Register (PTH)Read:Anytime.Write:Anytime.If the data direction bit

PIM_9DP256 Block User Guide V02.0736Write:Anytime.This register configures each port H pin as either input or output.DDRH[7:0] — Data Direction Port H

PIM_9DP256 Block User Guide V02.07371 = Either a pull-up or pull-down device is enabled.0 = Pull-up or pull-down device is disabled.Figure 3-35 Port

PIM_9DP256 Block User Guide V02.0738Figure 3-37 Port H Interrupt Flag Register (PIFH)Read:Anytime.Write:Anytime.Each flag is set by an active edge on

PIM_9DP256 Block User Guide V02.0739The IIC function takes precedence over the general purpose I/O function associated with if enabled.If both CAN4 a

PIM_9DP256 Block User Guide V02.0744.6 Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PIM_9DP256 Block User Guide V02.0740Figure 3-41 Port J Reduced Drive Register (RDRJ)Read:Anytime.Write:Anytime.This register configures the drive str

PIM_9DP256 Block User Guide V02.0741Figure 3-43 Port J Polarity Select Register (PPSJ)Read:Anytime.Write:Anytime.This register serves a dual purpose

PIM_9DP256 Block User Guide V02.0742Figure 3-45 Port J Interrupt Flag Register (PIFJ)Read:Anytime.Write:Anytime.Each flag is set by an active edge on

PIM_9DP256 Block User Guide V02.0743Section 4 Functional Description4.1 GeneralEach pin can act as general purpose I/O. In addition the pin can act

PIM_9DP256 Block User Guide V02.0744Figure 4-1 Illustration of I/O pin functionality4.1.4 Reduced drive registerIf the port is used as an output the

PIM_9DP256 Block User Guide V02.07454.3 Port SThis port is associated with the serial SCI and SPI modules.In all modes, port S pins PS[7:0] can be u

PIM_9DP256 Block User Guide V02.0746CAN0 has priority over CAN4 if both modules are trying to access PM[5:4] at the same time and CAN2is not enabled.T

PIM_9DP256 Block User Guide V02.0747Figure 4-2 Interrupt Glitch Filter on Port P, H and J (PPS=0)Table 4-2 Pulse Detection CriteriaFigure 4-3 Puls

PIM_9DP256 Block User Guide V02.0748Sample count <= 4 and port interrupt enabled (PIE=1) and port interrupt flag not set (PIF=0).4.6 Port HPort H

PIM_9DP256 Block User Guide V02.07494.10.3 Stop ModeAll clocks are stopped. There are asynchronous paths to generate interrupts from STOP on port P,

PIM_9DP256 Block User Guide V02.075List of FiguresFigure 1-1 PIM_9DP256 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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PIM_9DP256 Block User Guide V02.0751Section 5 Resets5.1 GeneralThe reset values of all registers are given in section 3.3 Register Descriptions.5.2

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PIM_9DP256 Block User Guide V02.0753Section 6 Interrupts6.1 GeneralPort P, H and J generate a separate edge sensitive interrupt if enabled.6.2 Int

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PIM_9DP256 Block User Guide V02.0755User Guide End Sheet

PIM_9DP256 Block User Guide V02.0756FINAL PAGE OF56PAGES

PIM_9DP256 Block User Guide V02.076Figure 3-33 Port H Reduced Drive Register (RDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Fig

PIM_9DP256 Block User Guide V02.077List of TablesTable 2-1 Pin Functions and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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PIM_9DP256 Block User Guide V02.079Section 1 Introduction1.1 OverviewThe Port Integration Module establishes the interface between the peripheral m