Motorola CPU32 Manuel d'utilisateur télécharger pdf (Page 19)

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Introduction

1-8

M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL

MOTOROLA

1.2.4 Floating-Point Instruction Address Register (FPIAR)

The integer unit can be executing instructions while the FPU is simultaneously executing a

ﬂoating-point instruction. Additionally, the FPU can concurrently execute two ﬂoating-point

instructions. Because of this nonsequential instruction execution, the PC value stacked by

the FPU, in response to a ﬂoating-point exception trap, may not point to the offending

instruction.

For the subset of the FPU instructions that generate exception traps, the 32-bit FPIAR is

loaded with the logical address of the instruction before the processor executes it. The

ﬂoating-point exception handler can use this address to locate the ﬂoating-point instruction

that caused an exception. Since the FPU FMOVE to/from the FPCR, FPSR, or FPIAR and

FMOVEM instructions cannot generate ﬂoating- point exceptions, these instructions do not

modify the FPIAR. A reset or a null-restore operation clears the FPIAR.

1.3 SUPERVISOR PROGRAMMING MODEL

System programers use the supervisor programming model to implement sensitive

operating system functions—e.g., I/O control and memory management unit (MMU)

subsystems. The following paragraphs brieﬂy describe the registers in the supervisor

programming model. They can only be accessed via privileged instructions. Table 1-1 lists

the supervisor registers and the processors not related to paged memory management. For

information concerning page memory management programming, refer to the device-

speciﬁc user’s manual. Table 1-2 lists the supervisor registers and the processors related to

paged memory management.

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Motorola CPU32 Manuel d'utilisateur Page 19

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