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Supervisor (Privileged) Instructions

6-38 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

PFLUSH PFLUSH

PFLUSHA PFLUSHA

PFLUSHS Invalidate Entries in the ATC PFLUSHS

(MC68851)

Operation: If Supervisor State

Then Address Translation Cache Entries For Destination Address

Are Invalidated

Else TRAP

Assembler PFLUSHA

Syntax: PFLUSH FC,MASK

PFLUSHS FC,MASK

PFLUSH FC,MASK, < ea >

PFLUSHS FC,MASK, < ea >

Attributes: Unsigned

Description: PFLUSHA invalidates all entries in the address translation cache.

PFLUSH invalidates a set of address translation cache entries whose function code

bits satisfy the relation: (address translation cache function code bits and mask) = (FC

and MASK) for all entries whose task alias matches the task alias currently active when

the instruction is executed. With an additional effective address argument, PFLUSH

invalidates a set of address translation cache entries whose function code satisfies the

relation above and whose effective address field matches the corresponding bits of the

evaluated effective address argument. In both of these cases, address translation

cache entries whose SG bit is set will not be invalidated unless the PFLUSHS is spec-

ified.

The function code for this operation may be specified as follows:

1. Immediate—The function code is four bits in the command word.

2. Data Register—The function code is in the lower four bits of the MC68020 data

3. Source Function Code (SFC) Register—The function code is in the CPU SFC

function codes $0D$7 can be speciﬁed in this manner.

4. Destination Function Code (DFC) Register—The function code is in the CPU

DFC register. Since the DFC of the MC68020 has only three implemented bits,

only function codes $0D$7 can be speciﬁed in this manner.

1 2 ... 196 197 198 199 200 201 202 203 204 205 206 ... 356 357

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Motorola M68000 Manuel d'utilisateur Page 201