Motorola MPC8260 Manuel d'utilisateur

MPC8260UM/D4/1999Rev. 0 MPC8260 PowerQUICC IIUserÕs Manualªª

x MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS ParagraphNumberTitlePageNumber 7.2.5.2 Address Retry (ARTRY)...

2-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewTable 2-1 shows the bit deÞnitions for HID0. Table 2-1. HID0 Field Descriptions Bits

Index-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXPPC_ALRL, 4-29programming model, 4-17registers, 4-17SCC relative priority, 4-12SCPRR_H, 4-19

MOTOROLA Index Index-21INDEXfractional stop bits, 20-11handling errors, 20-12hunt mode, 20-10memory map, 20-4normal asynchronous mode, 20-3overview,

Index-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEX

OverviewPowerPC Processor CoreMemory MapSystem Interface Unit (SIU)ResetExternal Signals60x SignalsThe 60x BusClocks and Power ControlMemory Controlle

OverviewPowerPC Processor CoreMemory MapSystem Interface Unit (SIU)ResetExternal Signals60x SignalsThe 60x BusClocks and Power ControlMemory Controlle

Attention!This book is a companion to the PowerPC Microprocessor Family: The ProgrammingEnvironments, referred to as The Programming Environments Manu

MOTOROLA Chapter 2. PowerPC Processor Core 2-13Part I. Overview11 DPM Dynamic power management enable. 10 Dynamic power management is disabled.1 Fu

2-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1)The MPC8260 implementat

MOTOROLA Chapter 2. PowerPC Processor Core 2-15Part I. OverviewFigure 2-4. Hardware Implementation Register 1 (HID1) Table 2-2 shows the bit deÞnit

2-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview2.3.1.2.4 Processor Version Register (PVR)Software can identify the MPC8260Õs proces

2-17 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview¥ Load/store instructionsÑThese include integer and ßoating-point load and store inst

2-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewComputational instructions do not modify memory. To use a memory operand in acomputat

MOTOROLA Chapter 2. PowerPC Processor Core 2-19Part I. OverviewPowerPC microprocessors control the following memory access modes on a page or block

2-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewFigure 2-6. Data Cache OrganizationBecause the processor core data cache tags are sin

MOTOROLA Chapter 2. PowerPC Processor Core 2-21Part I. Overviewmaximizing the efÞciency of the internal bus without sacriÞcing coherency of the dat

MOTOROLA Contents xi CONTENTS ParagraphNumberTitlePageNumber 8.4.3.1 Transfer Type Signal (TT[0Ð4]) Encoding ...

2-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overviewways 0, 1, and 2 but it is not possible to lock just way0 and way2). When using way l

MOTOROLA Chapter 2. PowerPC Processor Core 2-23Part I. Overviewan instruction-caused exception in the exception handler. SRR0 and SRR1 should also

2-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewAlthough exceptions have other characteristics as well, such as whether they are mask

MOTOROLA Chapter 2. PowerPC Processor Core 2-25Part I. OverviewISI 00400 An ISI exception is caused when an instruction fetch cannot be performed f

2-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview2.5.3 Exception PrioritiesThe exception priorities for the processor core are unchan

MOTOROLA Chapter 2. PowerPC Processor Core 2-27Part I. Overview2.6.1 PowerPC MMU ModelThe primary functions of the MMU are to translate logical (e

2-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview2.6.2 MPC8260 Implementation-SpeciÞc MMU FeaturesThe instruction and data MMUs in th

MOTOROLA Chapter 2. PowerPC Processor Core 2-29Part I. Overview2.7 Instruction TimingThe processor core is a pipelined superscalar processor. A pi

2-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewThe new latency is reßected in Table 2-6.2.8 Differences between the MPC8260Õs Core

MOTOROLA Chapter 2. PowerPC Processor Core 2-31Part I. OverviewAddition of speed-for-power functionalityThe processor core implements an additional

xii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS ParagraphNumberTitlePageNumber 9.8 System Clock Control Register (SCCR) ...

2-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview

MOTOROLA Chapter 3. Memory Map 3-1Chapter 3 Memory Map3030The MPC8260's internal memory resources are mapped within a contiguous block ofmemo

3-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview10030 PPC_ALRL 60x bus arbitration-level register low (next 8 clients)32 bits 4.3.2.3/

MOTOROLA Chapter 3. Memory Map 3-3Part I. Overview10134 OR6 Option register bank 6 32 bits 10.3.2/10-1610138 BR7 Base register bank 7 32 bits 10.3.

3-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewSystem Integration Timers10200Ð10 21F Reserved Ñ 32 bytes10220 TMCNTSC Time counter st

MOTOROLA Chapter 3. Memory Map 3-5Part I. OverviewInput/Output Port10D00 PDIRA Port A data direction register 32 bits 35.2.3/35-310D04 PPARA Port A

3-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview10D92 TMR2 Timer 2 mode register 16 bits 17.2.3/17-610D94 TRR1 Timer 1 reference regis

MOTOROLA Chapter 3. Memory Map 3-7Part I. Overview11029 Reserved Ñ 24 bits Ñ1102C IDMR2 IDMA 2 mask register 8 bits 18.8.4/18-221102D Reserved Ñ 24

3-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview11328 FTODR2 FCC2 transmit on-demand register 16 bits 28.5/28-71132A Reserved Ñ 2 byt

MOTOROLA Chapter 3. Memory Map 3-9Part I. OverviewI2C11860 I2MOD I2C mode register 8 bits 34.4.1/34-611862 Reserved Ñ 24 bits Ñ11864 I2ADD I2C addr

MOTOROLA Contents xiii CONTENTS ParagraphNumberTitlePageNumber 10.4.5 Bank Interleaving ...

3-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview11A08 PSMR1 SCC1 protocol-speciÞc mode register 16 bits 19.1.2/19-920.16/20-13 (UART)

MOTOROLA Chapter 3. Memory Map 3-11Part I. OverviewSCC311A40 GSMR_L3 SCC3 general mode register 32 bits 19.1.1/19-311A44 GSMR_H3 SCC3 general mode

3-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview11A77 SCCS4 SCC4 status register 8 bits 20.20/20-21 (UART)21.12/21-14 (HDLC)22.15/22-

MOTOROLA Chapter 3. Memory Map 3-13Part I. Overview11B0E CMXUAR CPM mux UTOPIA address register 16 bits 15.4.1/15-711B10Ð11B1F Reserved Ñ 16 bytes

3-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewMCC2 Registers11B50 MCCE2 MCC2 event register 16 bits 27.10.1/27-1811B54 MCCM2 MCC2 m

MOTOROLA Part II. Configuration and Reset Part II-iPart IIConÞguration and ResetAudiencePart II is intended for system designers and programmers w

Part II-ii MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. Configuration and ResetConventionsThis chapter uses the following notational conventio

MOTOROLA Part II. Configuration and Reset Part II-iiiPart II. Configuration and Resetmsb Most-signiÞcant bitMSR Machine state register PCI Periphe

Part II-iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. Configuration and Reset

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-1Chapter 4 System Interface Unit (SIU)4040The system interface unit (SIU) consists of several fu

xiv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS ParagraphNumberTitlePageNumber 10.6.4.1.4 Loop Control ...

4-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetThe system conÞguration and protection functions provide various monito

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-3Part II. ConÞguration and ResetFigure 4-2 is a block diagram of the system conÞguration and prot

4-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset4.1.2 Timers ClockThe two SIU timers (the time counter and the periodi

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-5Part II. ConÞguration and ResetFigure 4-4. TMCNT Block DiagramSection 4.3.2.15, ÒTime Counter Re

4-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetThe time-out period is calculated as follows:This gives a range from 12

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-7Part II. ConÞguration and ResetAlthough most software disciplines permit or even encourage the w

4-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset¥ Two priority schemes for the SCCs: grouped, spread¥ Programmable high

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-9Part II. ConÞguration and ResetIf the software watchdog timer is programmed to generate an inter

4-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset5 XSIU4 (GSIU = 0) No (TMCNT,PIT = Yes)6 XCC1 Yes7 XCC2 Yes8 XCC3 Yes9

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-11Part II. ConÞguration and Reset34 SDMA Bus Error Yes35 IDMA1 Yes36 YCC2 (Spread) Yes37 Parallel

MOTOROLA Contents xv CONTENTS ParagraphNumberTitlePageNumber 12.5 MPC8260 Restrictions ...

4-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetNotice the lack of SDMA interrupt sources, which are reported through

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-13Part II. ConÞguration and Reset4.2.2.3 Highest Priority InterruptIn addition to the FCC/MCC/SC

4-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetFigure 4-9. Interrupt Request Masking4.2.4 Interrupt Vector Generatio

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-15Part II. ConÞguration and Reset6 IDMA1 0b00_01107 IDMA2 0b00_01118 IDMA3 0b00_10009 IDMA4 0b00_

4-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetNote that the interrupt vector table differs from the interrupt priori

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-17Part II. ConÞguration and Reset4.3 Programming ModelThe SIU registers are grouped into the fol

4-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetThe SICR register bits are described in Table 4-4.4.3.1.2 SIU Interru

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-19Part II. ConÞguration and ResetThe SIPRR register bits are described in Table 4-5.4.3.1.3 CPM

4-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetTable 4-6 describes SCPRR_H Þelds.The CPM low interrupt priority regis

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-21Part II. ConÞguration and Reset4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L) E

xvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS ParagraphNumberTitlePageNumberChapter 14 Serial Interface with Time-Slot Assigner 14.1

4-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetWhen a pending interrupt is handled, the user clears the corresponding

4-23 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetNote the following:¥ SCC/MCC/FCC SIMR bit positions are not affected b

4-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetThe SIVEC can be read as either a byte, half word, or a word. When rea

4-25 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II. ConÞguration and Reset Table 4-8 describes SIEXR Þelds. 4.3.2 System ConÞguration and Pro

4-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II. ConÞguration and Reset Table 4-9 describes BCR Þelds. Bits0 1 2 3 4 5 6 7 8 9 10 11 12 13

4-27 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II. ConÞguration and Reset 13 LETM Local bus compatibility mode enable. See Section 8.4.3.8, Ò

4-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II. ConÞguration and Reset 4.3.2.2 60x Bus Arbiter ConÞguration Register (PPC_ACR) The 60x bu

4-29 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II. ConÞguration and Reset PPC_ALRL, shown in Figure 4-24, deÞnes arbitration priority of 60x

4-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II. ConÞguration and Reset Table 4-11 describes LCL_ACR register bits. 4.3.2.5 Local Bus Arbi

4-31 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset4.3.2.6 SIU Module ConÞguration Register (SIUMCR)The SIU module conÞ

MOTOROLA Contents xvii CONTENTS ParagraphNumberTitlePageNumberChapter 16 Baud-Rate Generators (BRGs) 16.1 BRG Configuration Registers 1Ð8 (BRGCx)

4-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetTable 4-12 describes SIUMCR Þelds.Table 4-12. SIUMCR Register Field De

4-33 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset10Ð11 APPC Address parity pins conÞguration. Note that during power on

4-34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset4.3.2.7 Internal Memory Map Register (IMMR)The internal memory map re

4-35 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset4.3.2.8 System Protection Control Register (SYPCR)The system protecti

4-36 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset4.3.2.9 Software Service Register (SWSR)The software service register

4-37 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2

4-38 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetThe TESCR2 register is described in Table 4-16.4.3.2.12 Local Bus Tra

4-39 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetThe L_TESCR1 register bits are described in Table 4-17.4.3.2.13 Local

4-40 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetTable 4-18 describes L_TESCR2 Þelds.4.3.2.14 Time Counter Status and

4-41 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset4.3.2.15 Time Counter Register (TMCNT)The time counter register (TMCN

xviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS ParagraphNumberTitlePageNumber 18.5.3 Controlling 60x Bus Bandwidth...

4-42 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetTable 4-20 describes TMCNTAL Þelds.4.3.3 Periodic Interrupt Registers

4-43 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetTable 4-21 describes PISCR Þelds.4.3.3.2 Periodic Interrupt Timer Cou

4-44 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetTable 4-22 describes PITC Þelds.4.3.3.3 Periodic Interrupt Timer Regi

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-45Part II. ConÞguration and ResetTable 4-24.Table 4-24. SIU Pins Multiplexing Control Pin Name Pi

4-46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset

MOTOROLA Chapter 5. Reset 5-1Chapter 5 Reset5050The MPC8260 has several inputs to the reset logic:¥ Power-on reset (PORESET)¥ External hard reset

5-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset5.1.1 Reset ActionsThe reset block has a reset control logic that dete

MOTOROLA Chapter 5. Reset 5-3Part II. ConÞguration and ResetFigure 5-3 shows the power-on reset ßow.5.1.3 HRESET FlowThe HRESET ßow may be initia

5-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset5.2 Reset Status Register (RSR)The reset status register (RSR), shown

MOTOROLA Chapter 5. Reset 5-5Part II. ConÞguration and ResetNote that RSR accumulates reset events. For example, because software watchdogexpirati

MOTOROLA Contents xix CONTENTS ParagraphNumberTitlePageNumber 19.3.5.2 Asynchronous Protocols ...

5-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset5.4 Reset ConÞgurationVarious features may be conÞgured during hard re

MOTOROLA Chapter 5. Reset 5-7Part II. ConÞguration and ResetTable 5-6 shows addresses that should be used to conÞgure the various MPC8260s. Bytead

5-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and Reset5.4.1 Hard Reset ConÞguration WordThe contents of the hard reset conÞg

MOTOROLA Chapter 5. Reset 5-9Part II. ConÞguration and Reset5.4.2 Hard Reset ConÞguration ExamplesThis section presents some examples of hard res

5-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetFigure 5-4. Single Chip with Default Configuration5.4.2.2 Single MPC8

MOTOROLA Chapter 5. Reset 5-11Part II. ConÞguration and ResetFigure 5-6. Configuring Multiple ChipsPORESETPORESETPORESETPORESETA0A1A6HRESETHRESETH

5-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart II. ConÞguration and ResetIn this system, the conÞguration master initially reads its own conÞgu

MOTOROLA Part III. The Hardware Interface Part III-iPart IIIThe Hardware InterfaceIntended AudiencePart III is intended for system designers who ne

Part III-ii MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceSuggested ReadingThis section lists additional reading that pr

MOTOROLA Part III. The Hardware Interface Part III-iiiPart III. The Hardware Interfacen Indicates an undeÞned numerical value NOT logical operator

PowerQUICC II, Mfax, and DigitalDNA are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e,

xx MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS ParagraphNumberTitlePageNumberChapter 21 SCC HDLC Mode 21.1 SCC HDLC Features ...

Part III-iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceLSB Least-signiÞcant bytelsb Least-signiÞcant bitLSU Load/stor

MOTOROLA Part III. The Hardware Interface Part III-vPart III. The Hardware InterfaceUISA User instruction set architectureUPM User-programmable mac

Part III-vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface

MOTOROLA Chapter 6. External Signals 6-1Chapter 6 External Signals6060This chapter describes the MPC8260 external signals. A more detailed descrip

6-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 6-1. MPC8260 External Signals6.2 Signal DescriptionsThe MPC826

MOTOROLA Chapter 6. External Signals 6-3Part III. The Hardware InterfaceTable 6-1. External Signals Signal DescriptionBR60x bus requestÑThis is an

6-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceDBBIRQ360x data bus busyÑ(Input/output)As an output the MPC8260 assert

MOTOROLA Chapter 6. External Signals 6-5Part III. The Hardware InterfaceIRQ5DP[5]TBENEXT_DBG3Interrupt request 5ÑThis input is one of the eight ext

6-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceWTBADDR30IRQ3Write throughÑOutput used for L2 cache control. For each

MOTOROLA Chapter 6. External Signals 6-7Part III. The Hardware InterfaceBADDR[27Ð28] Burst address 27:28ÑThere are Þve burst address output pins. T

MOTOROLA Contents xxi CONTENTS ParagraphNumberTitlePageNumber 22.12 SCC BISYNC Receive BD (RxBD) ...

6-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceLWE[0Ð3]LSDDQM[0Ð3]LBS[0Ð3]Local bus write enableÑThe write enable pin

MOTOROLA Chapter 6. External Signals 6-9Part III. The Hardware InterfaceL_A15SMIPCI_FRAMELocal bus address 15ÑLocal bus address bit 15 output pin.

6-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceL_A24PCI_REQ1Local bus address 24ÑLocal bus address bit 24 output pin

MOTOROLA Chapter 6. External Signals 6-11Part III. The Hardware InterfaceLCL_DP[0Ð3]PCI_C/BE[0Ð3]Local bus data parityÑLocal bus data parity input/

6-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceNote that CPM port multiplexing is described in the Chapter 35, ÒPara

MOTOROLA Chapter 7. 60x Signals 7-1Chapter 7 60x Signals7070This chapter describes the MPC8260 PowerPC processorÕs external signals. It contains a

7-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface¥ Data transfer signalsÑThese signals, which consist of the data bus,

MOTOROLA Chapter 7. 60x Signals 7-3Part III. The Hardware Interface7.2 Signal Descriptions This section describes individual MPC8260 60x signals,

7-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface7.2.1.1.2 Address Bus Request (BR)ÑInputFollowing are the state meani

MOTOROLA Chapter 7. 60x Signals 7-5Part III. The Hardware InterfaceNegationÑMay occur whenever the MPC8260 must be prevented from using the address

xxii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS ParagraphNumberTitlePageNumber 24.6 The Content-Addressable Memory (CAM) Interface ...

7-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface7.2.1.3.2 Address Bus Busy (ABB)ÑInputFollowing are the state meaning

MOTOROLA Chapter 7. 60x Signals 7-7Part III. The Hardware InterfaceTiming Comments Assertion/NegationÑMust be asserted for one cycle only and then

7-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface7.2.4.1 Transfer Type (TT[0Ð4])The transfer type signals (TT[0Ð4]) c

MOTOROLA Chapter 7. 60x Signals 7-9Part III. The Hardware InterfaceHigh ImpedanceÑSame as A[0Ð31].7.2.4.4 Global (GBL)The global (GBL) signal is a

7-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceNegatedÑIndicates that the transaction should not operate in write-th

MOTOROLA Chapter 7. 60x Signals 7-11Part III. The Hardware Interface7.2.5.2 Address Retry (ARTRY)The address retry (ARTRY) signal is both an input

7-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface7.2.6 Data Bus Arbitration SignalsThe data bus arbitration signals h

MOTOROLA Chapter 7. 60x Signals 7-13Part III. The Hardware Interface7.2.6.2 Data Bus Busy (DBB)The data bus busy (DBB) signal is both an input and

7-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface7.2.7.1.1 Data Bus (D[0Ð63])ÑOutputFollowing are the state meaning a

MOTOROLA Chapter 7. 60x Signals 7-15Part III. The Hardware InterfaceTiming Comments Assertion/NegationÑThe same as the data bus. High ImpedanceÑThe

MOTOROLA Contents xxiii CONTENTS ParagraphNumberTitlePageNumber26.2.4.4 SMC Receiver Shortcut Sequence ...

7-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceNegatedÑ(During assertion of DBB) indicates that, until TA is asserte

MOTOROLA Chapter 7. 60x Signals 7-17Part III. The Hardware InterfaceNegatedÑIndicates that no bus error was detected. Timing Comments AssertionÑMay

7-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interfacesystem can assert PSDVAL for one bus clock cycle and then negate it t

MOTOROLA Chapter 8. The 60x Bus 8-1Chapter 8 The 60x Bus8080The 60x bus, which is used by PowerPC processors, provides ßexible support for the on-

8-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface8.2 Bus ConÞgurationThe 60x bus supports separate bus conÞgurations f

MOTOROLA Chapter 8. The 60x Bus 8-3Part III. The Hardware InterfaceFigure 8-1. Single MPC8260 Bus Mode Note that in single MPC8260 bus mode, the MP

8-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 8-2. 60x-Compatible Bus Mode8.3 60x Bus Protocol OverviewTypic

MOTOROLA Chapter 8. The 60x Bus 8-5Part III. The Hardware InterfacedeÞned by the 60x bus speciÞcation. For more information, see Section 8.5.5, ÒPo

8-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interfaceexternal central bus arbiter or by the internal on-chip arbiter. In th

MOTOROLA Chapter 8. The 60x Bus 8-7Part III. The Hardware Interface8.3.2 Address Pipelining and Split-Bus TransactionsThe 60x bus protocol provide

xxiv MPC8260 PowerQUICC II UserÕs Manual MOTOROLACONTENTSParagraphNumberTitlePageNumberChapter 27 Multi-Channel Controllers (MCCs)27.1 Features...

8-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interfacetransaction, it skips the bus request delay and assumes address bus ma

MOTOROLA Chapter 8. The 60x Bus 8-9Part III. The Hardware InterfaceFigure 8-4. Address Bus Arbitration with External Bus Master8.4.2 Address Pipel

8-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 8-5. Address Pipelining 8.4.3 Address Transfer Attribute Sign

MOTOROLA Chapter 8. The 60x Bus 8-11Part III. The Hardware Interface01000 sync Address onlyAddress only (if enabled)sync (if enabled) Not applicabl

8-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceNote the following regarding Table 8-2:¥ For reads, the processor cle

MOTOROLA Chapter 8. The 60x Bus 8-13Part III. The Hardware Interface8.4.3.2 Transfer Code Signals TC[0Ð2] The transfer code signals, TC[0Ð2], prov

8-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceNote that the basic coherency size of the bus is 32 bytes for the pro

MOTOROLA Chapter 8. The 60x Bus 8-15Part III. The Hardware Interface The MPC8260 supports misaligned memory operations, although they may degradepe

8-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interfacesoftware attempt to align code and data where possible. 8.4.3.6 Effe

MOTOROLA Chapter 8. The 60x Bus 8-17Part III. The Hardware InterfaceFigure 8-6. Interface to Different Port Size Devices031 63OP0 OP1 OP2 OP3 OP4 O

MOTOROLA Contents xxvCONTENTSParagraphNumberTitlePageNumber28.8.3 FCC Status Registers (FCCSx) ...

8-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceTable 8-9 lists data transfer patterns for write cycles for accesses

MOTOROLA Chapter 8. The 60x Bus 8-19Part III. The Hardware Interface8.4.3.7 60x-Compatible Bus ModeÑSize CalculationTo comply with the requirement

8-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface8.4.3.8 Extended Transfer ModeThe MPC8260 supports an extended trans

MOTOROLA Chapter 8. The 60x Bus 8-21Part III. The Hardware Interfacebus, but some slaves or masters do not support these features. Clear BCR[ETM] t

8-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceExtended transfer mode is enabled by setting the BCR[ETM].Table 8-13.

MOTOROLA Chapter 8. The 60x Bus 8-23Part III. The Hardware Interface8.4.4 Address Transfer TerminationAddress transfer termination occurs with the

8-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 8-7. Retry CycleAs a bus master, the MPC8260 recognizes either

MOTOROLA Chapter 8. The 60x Bus 8-25Part III. The Hardware Interfacealso detect this event and abort any transfer in progress. If this TA/ARTRY rel

8-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface8.4.5 Pipeline ControlThe MPC8260 supports the two following modes:¥

MOTOROLA Chapter 8. The 60x Bus 8-27Part III. The Hardware Interfacefollowing cycle. In case the external arbiter asserts DBG on the cycle in which

xxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLACONTENTSParagraphNumberTitlePageNumber29.3.6 Determining the Priority of an ATM Channel ...

8-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface¥ Asserting ARTRY causes the data tenure to be terminated immediately

MOTOROLA Chapter 8. The 60x Bus 8-29Part III. The Hardware InterfaceFigure 8-9 shows an extended transaction of 4 words to a port size of 32 bits.

8-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 8-10. Burst Transfer to 32-Bit Port Size8.5.6 Data Bus Termin

MOTOROLA Chapter 8. The 60x Bus 8-31Part III. The Hardware InterfaceFigure 8-11. Data Tenure Terminated by Assertion of TEAMPC8260 interprets the f

8-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceWhen the MPC8260 processor is not the address bus master, GBL is an i

MOTOROLA Chapter 8. The 60x Bus 8-33Part III. The Hardware Interface8.7.1 Support for the lwarx/stwcx. Instruction PairThe load word and reserve i

8-34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface

MOTOROLA Chapter 9. Clocks and Power Control 9-1Chapter 9 Clocks and Power Control9090The MPC8260Õs clocking architecture includes two PLLsÑthe ma

9-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface9.2 Clock ConÞgurationTo conÞgure the main PLL multiplication factor

MOTOROLA Chapter 9. Clocks and Power Control 9-3Part III. The Hardware Interface0010_011 33 MHz 4 133 MHz 5 166 MHz0010_100 33 MHz 4 133 MHz 6 200

MOTOROLA Contents xxviiCONTENTSParagraphNumberTitlePageNumber29.10.1.3 Global Mode Entry (GMODE) ...

9-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceBecause of speed dependencies, not all conÞgurations in Table 9-2 may

MOTOROLA Chapter 9. Clocks and Power Control 9-5Part III. The Hardware Interface9.3 External Clock InputsThe input clock source to the PLL is an e

9-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceThe direction selected depends on whether the feedback signal phase la

MOTOROLA Chapter 9. Clocks and Power Control 9-7Part III. The Hardware Interface9.6.1 General System ClocksThe general system clocks (CPM_CLK, CPM

9-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 9-2. PLL Filtering Circuit9.8 System Clock Control Register (S

MOTOROLA Chapter 9. Clocks and Power Control 9-9Part III. The Hardware Interface9.9 System Clock Mode Register (SCMR)The system clock mode registe

9-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceThe relationships among these parameters are described in the formula

MOTOROLA Chapter 10. Memory Controller 10-1Chapter 10 Memory Controller100100The memory controller is responsible for controlling a maximum of twe

10-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceThe MPC8260 supports the following new features as compared to the MP

MOTOROLA Chapter 10. Memory Controller 10-3Part III. The Hardware InterfaceFigure 10-1. Dual-Bus Architecture10.1 FeaturesThe memory controllerÕs

xxviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLACONTENTSParagraphNumberTitlePageNumber29.12.1 UTOPIA Interface Master Mode...

10-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceÑ Write-protection capabilityÑ Control signal generation machine sele

MOTOROLA Chapter 10. Memory Controller 10-5Part III. The Hardware InterfaceÑ Each UPM can be deÞned to support DRAM devices with depths of 64, 128,

10-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-2. Memory Controller Machine SelectionSome features are com

MOTOROLA Chapter 10. Memory Controller 10-7Part III. The Hardware InterfaceFigure 10-3. Simple System ConfigurationImplementation differences betwe

10-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interfaceselected according to the type of external access transacted. At ever

MOTOROLA Chapter 10. Memory Controller 10-9Part III. The Hardware Interface10.2.2 Page Hit CheckingThe SDRAM machine supports page-mode operation.

10-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.2.7 Data Buffer Controls (BCTLx)The memory controller provides t

MOTOROLA Chapter 10. Memory Controller 10-11Part III. The Hardware InterfaceNote that this feature cannot be used with L2 cacheable banks and that

10-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.2.13 Partial Data Valid Indication (PSDVAL)The 60x and local bus

MOTOROLA Chapter 10. Memory Controller 10-13Part III. The Hardware InterfaceFigure 10-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Wor

MOTOROLA Contents xxixCONTENTSParagraphNumberTitlePageNumber30.19 Ethernet RxBDs...

10-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.3.1 Base Registers (BRx)The base registers (BR0ÐBR11) contain th

MOTOROLA Chapter 10. Memory Controller 10-15Part III. The Hardware Interface23 WP Write protect. Can restrict write accesses within the address ran

10-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.3.2 Option Registers (ORx)The ORx registers deÞne the sizes of m

MOTOROLA Chapter 10. Memory Controller 10-17Part III. The Hardware Interface5Ð11 SDAM SDRAM address mask. Provides masking for corresponding bits i

10-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-8 shows ORx as it is formatted for GPCM mode. Table 10-5 d

10-19 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface21Ð22 ACS Address to chip select setup. Can be used when the externa

10-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-9 shows ORx as it is formatted for UPM mode.Table 10-6 des

MOTOROLA Chapter 10. Memory Controller 10-21Part III. The Hardware Interface10.3.3 60x SDRAM Mode Register (PSDMR)The 60x SDRAM mode register (PSD

10-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface8Ð10 BSMA Bank select multiplexed address line. Selects the address

MOTOROLA Chapter 10. Memory Controller 10-23Part III. The Hardware Interface23 BL Burst length0 SDRAM burst length is 4. Use this value if the devi

OverviewPowerPC Processor CoreMemory MapSystem Interface Unit (SIU)ResetExternal Signals60x SignalsThe 60x BusClocks and Power ControlMemory Controll

xxx MPC8260 PowerQUICC II UserÕs Manual MOTOROLACONTENTSParagraphNumberTitlePageNumber33.4.3 SPI Command Register (SPCOM) ...

10-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.3.4 Local Bus SDRAM Mode Register (LSDMR)The LSDMR, shown in Fig

MOTOROLA Chapter 10. Memory Controller 10-25Part III. The Hardware InterfaceSDRAM DeviceÐSpeciÞc Parameters:14Ð16 RFRC Refresh recovery. DeÞnes the

10-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.3.5 Machine A/B/C Mode Registers (MxMR)The machine x mode regist

MOTOROLA Chapter 10. Memory Controller 10-27Part III. The Hardware InterfaceTable 10-9 describes MxMR bits.Table 10-9. Machine x Mode Registers (Mx

10-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.3.6 Memory Data Register (MDR)The memory data register (MDR), sh

MOTOROLA Chapter 10. Memory Controller 10-29Part III. The Hardware InterfaceTable 10-10 describes MDR Þelds. 10.3.7 Memory Address Register (MAR)T

10-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceTable 10-11 describes MAR Þelds.10.3.8 60x Bus-Assigned UPM Refresh

MOTOROLA Chapter 10. Memory Controller 10-31Part III. The Hardware InterfaceTable 10-13 describes LURT Þelds. 10.3.10 60x Bus-Assigned SDRAM Refre

10-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)The local bus-

MOTOROLA Chapter 10. Memory Controller 10-33Part III. The Hardware Interface10.3.13 60x Bus Error Status and Control Registers (TESCRx)These regis

MOTOROLA Contents xxxiCONTENTSParagraphNumberTitlePageNumber35.2.3 Port Data Direction Registers (PDIRAÐPDIRD)...

10-34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceyFigure 10-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 an

MOTOROLA Chapter 10. Memory Controller 10-35Part III. The Hardware Interface10.4.1 Supported SDRAM ConÞgurationsThe MPC8260 memory controller supp

10-36 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.4.4 Page-Mode Support and Pipeline AccessesThe SDRAM interface s

MOTOROLA Chapter 10. Memory Controller 10-37Part III. The Hardware InterfaceThe following two methods are used for internal bank interleaving:¥ Pa

10-38 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceTable 10-20 shows SDRAM address multiplexing for A16ÐA31.10.4.6 SDR

MOTOROLA Chapter 10. Memory Controller 10-39Part III. The Hardware InterfaceFigure 10-20. PRETOACT = 2 (2 Clock Cycles)10.4.6.2 Activate to Read/W

10-40 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.4.6.3 Column Address to First Data OutÑCAS Latency This paramete

MOTOROLA Chapter 10. Memory Controller 10-41Part III. The Hardware Interface10.4.6.5 Last Data In to PrechargeÑWrite Recovery This parameter, cont

10-42 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interfaceshould be set. Setting this bit causes the memory controller to add

MOTOROLA Chapter 10. Memory Controller 10-43Part III. The Hardware InterfaceFigure 10-28. SDRAM Single-Beat Read, Page Closed, CL = 3Figure 10-29.

xxxii MPC8260 PowerQUICC II UserÕs Manual MOTOROLACONTENTSParagraphNumberTitlePageNumber

10-44 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3Figure 10

MOTOROLA Chapter 10. Memory Controller 10-45Part III. The Hardware InterfaceFigure 10-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3Figure 10

10-46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.4.8 SDRAM Read/Write TransactionsThe SDRAM interface supports th

MOTOROLA Chapter 10. Memory Controller 10-47Part III. The Hardware InterfaceFigure 10-38. Mode Data Bit Settings10.4.10 SDRAM RefreshThe memory co

10-48 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-39. SDRAM Bank-Staggered CBR Refresh Timing10.4.12 SDRAM

MOTOROLA Chapter 10. Memory Controller 10-49Part III. The Hardware InterfaceNow, from the SDRAM device point of view, during an ACTIVATE command, i

10-50 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.4.13 SDRAM ConÞguration Example (Bank-Based Interleaving)Conside

MOTOROLA Chapter 10. Memory Controller 10-51Part III. The Hardware Interface10.5 General-Purpose Chip-Select Machine (GPCM)Users familiar with the

10-52 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-40. GPCM-to-SRAM ConÞguration10.5.1 Timing ConÞgurationIf

MOTOROLA Chapter 10. Memory Controller 10-53Part III. The Hardware Interface10.5.1.1 Chip-Select Assertion Timing From 0 to 30 wait states can be

MOTOROLA Illustrations xxxiiiILLUSTRATIONSFigureNumberTitle Page Number1-1 MPC8260 Block Diagram ...

10-54 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.5.1.2 Chip-Select and Write Enable Deassertion Timing Figure 10-

MOTOROLA Chapter 10. Memory Controller 10-55Part III. The Hardware InterfaceFigure 10-45. GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX

10-56 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface Figure 10-47. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT =

MOTOROLA Chapter 10. Memory Controller 10-57Part III. The Hardware Interface Figure 10-49. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1,

10-58 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-50 through Figure 10-53 show timing examples. Figure 10-50

MOTOROLA Chapter 10. Memory Controller 10-59Part III. The Hardware Interface Figure 10-51. GPCM Read Followed by Read (ORx[29Ð30] = 01) Figure 10-5

10-60 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface Figure 10-53. GPCM Read Followed by Read (ORx[29Ð30] = 10)10.5.2 E

MOTOROLA Chapter 10. Memory Controller 10-61Part III. The Hardware InterfaceFigure 10-54. External Termination of GPCM Access10.5.3 Boot Chip-Sele

10-62 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.5.4 Differences between MPC8xxÕs GPCM and MPC8260Õs GPCMUsers fa

MOTOROLA Chapter 10. Memory Controller 10-63Part III. The Hardware InterfaceAdditional control is available in 60x-compatible mode (60x bus only)ÑA

xxxiv MPC8260 PowerQUICC II UserÕs Manual MOTOROLAILLUSTRATIONSFigureNumberTitlePageNumber4-20 SIU External Interrupt Control Register (SIEXR)...

10-64 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceNote that 60x bus accesses that hit a bank allocated to the local bu

MOTOROLA Chapter 10. Memory Controller 10-65Part III. The Hardware InterfaceTable 10-34 show the start address of each pattern.10.6.1.1 Memory Acc

10-66 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceAll local bus refreshes are done using the refresh pattern of UPMB.

MOTOROLA Chapter 10. Memory Controller 10-67Part III. The Hardware Interface3. Program MPTPR and L/PSRT if refresh is required.4. Program the machi

10-68 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-59. Memory Controller UPM Clock Scheme for Non-Integer (2.

MOTOROLA Chapter 10. Memory Controller 10-69Part III. The Hardware InterfaceFigure 10-60. UPM Signals Timing Example 10.6.4 The RAM ArrayThe RAM a

10-70 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-61. RAM Array and Signal Generation10.6.4.1 RAM WordsThe

MOTOROLA Chapter 10. Memory Controller 10-71Part III. The Hardware InterfaceTable 10-35 describes RAM word Þelds. Table 10-35. RAM Word Bit Setting

10-72 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface12 G1T1 General-purpose line 1 timing 1. DeÞnes the state of GPL1 du

MOTOROLA Chapter 10. Memory Controller 10-73Part III. The Hardware Interface20 G5T1 General-purpose line 5 timing 1. DeÞnes the state of GPL5 durin

MOTOROLA Illustrations xxxvILLUSTRATIONSFigureNumberTitlePageNumber9-3 System Clock Control Register (SCCR)...

10-74 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceAdditional information about some of the RAM word Þelds is provided

MOTOROLA Chapter 10. Memory Controller 10-75Part III. The Hardware InterfaceFigure 10-63. CS Signal Selection10.6.4.1.2 Byte-Select Signals (BxTx)

10-76 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.6.4.1.3 General-Purpose Signals (GxTx, GOx)The general-purpose s

MOTOROLA Chapter 10. Memory Controller 10-77Part III. The Hardware InterfaceFigure 10-79 shows an example of REDO use.10.6.4.2 Address Multiplexin

10-78 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-65. UPM Read Access Data Sampling10.6.4.4 Signals Negatio

MOTOROLA Chapter 10. Memory Controller 10-79Part III. The Hardware InterfaceFigure 10-66. Wait Mechanism Timing for Internal and External Synchrono

10-80 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceThis means that the address bus should be partitioned as shown in Ta

MOTOROLA Chapter 10. Memory Controller 10-81Part III. The Hardware Interface¥ Timing of GPL[0Ð5]ÑIn the MPC8xxÕs UPM, the GPL lines could change on

10-82 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-67. DRAM Interface Connection to the 60x Bus (64-Bit Port

MOTOROLA Chapter 10. Memory Controller 10-83Part III. The Hardware InterfaceMxMR[OP] = 11. Figure 10-56 shows the Þrst locations addressed by the U

xxxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLAILLUSTRATIONSFigureNumberTitlePageNumber10-41 GPCM Peripheral Device Interface ...

10-84 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-69. Single-Beat Write Access to FPM DRAMcst1 0 0 0 Bit 0cs

MOTOROLA Chapter 10. Memory Controller 10-85Part III. The Hardware InterfaceFigure 10-70. Burst Read Access to FPM DRAM (No LOOP)cst1 000000000 Bit

10-86 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-71. Burst Read Access to FPM DRAM (LOOP)cst1 0 0 0 Bit 0cs

MOTOROLA Chapter 10. Memory Controller 10-87Part III. The Hardware InterfaceFigure 10-72. Burst Write Access to FPM DRAM (No LOOP)cst1 000000000 Bi

10-88 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-73. Refresh Cycle (CBR) to FPM DRAMcst1 1 0 0 Bit 0cst2 1

MOTOROLA Chapter 10. Memory Controller 10-89Part III. The Hardware InterfaceFigure 10-74. Exception Cyclecst1 1 Bit 0cst2 1 Bit 1cst3 1 Bit 2cst4 1

10-90 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface¥ If GPL_4 is not used as an output, the performance for a page read

MOTOROLA Chapter 10. Memory Controller 10-91Part III. The Hardware InterfaceFigure 10-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge

10-92 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.7.0.1 EDO Interface ExampleFigure 10-76 shows a memory connectio

MOTOROLA Chapter 10. Memory Controller 10-93Part III. The Hardware InterfaceFigure 10-77. Single-Beat Read Access to EDO DRAMcst1 00000 Bit 0cst2 0

MOTOROLA Illustrations xxxviiILLUSTRATIONSFigureNumberTitlePageNumber10-82 Refresh Cycle (CBR) to EDO DRAM...

10-94 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-78. Single-Beat Write Access to EDO DRAMcst1 0001 Bit 0cst

MOTOROLA Chapter 10. Memory Controller 10-95Part III. The Hardware Interface Figure 10-79. Single-Beat Write Access to EDO DRAM Using REDO to Inse

10-96 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-80. Burst Read Access to EDO DRAMcst1 00000000000Bit 0cst2

MOTOROLA Chapter 10. Memory Controller 10-97Part III. The Hardware InterfaceFigure 10-81. Burst Write Access to EDO DRAMcst1 0000000000 Bit 0cst2 0

10-98 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-82. Refresh Cycle (CBR) to EDO DRAMcst1 10001 Bit 0cst2 10

MOTOROLA Chapter 10. Memory Controller 10-99Part III. The Hardware InterfaceFigure 10-83. Exception Cycle For EDO DRAMcst1 1 Bit 0cst2 1 Bit 1cst3

10-100 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface10.8 Handling Devices with Slow or Variable Access Times The memor

MOTOROLA Chapter 10. Memory Controller 10-101Part III. The Hardware Interface10.9 External Master Support (60x-Compatible Mode)The memory controll

10-102 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface¥ PSDVAL as a termination to a partial transaction (such as port-si

MOTOROLA Chapter 10. Memory Controller 10-103Part III. The Hardware InterfaceThe 60x bus is pipelined. The ALE pins control the external latch that

xxxviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLAILLUSTRATIONSFigureNumberTitlePageNumber14-17 Falling Edge (FE) Effect When CE = 0 and xFSD = 00 .

10-104 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 10-85 shows the 1-cycle delay for external master access. Fo

MOTOROLA Chapter 10. Memory Controller 10-105Part III. The Hardware InterfaceFigure 10-86. External Master Configuration with SDRAM DeviceSDAMUXTT[

10-106 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface

MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-1Chapter 11 Secondary (L2) Cache Support110110The MPC8260 has features to support an external

11-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 11-1. L2 Cache in Copy-Back Mode11.1.2 Write-Through ModeIn w

MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-3Part III. The Hardware Interfaceare serviced just as they are for copy-back mode. Write-throu

11-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 11-2. External L2 Cache in Write-Through Mode11.1.3 ECC/Parit

MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-5Part III. The Hardware InterfaceIn ECC/parity mode the L2 cache can support memory regions wi

11-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 11-3. External L2 Cache in ECC/Parity ModeTS, TT[0Ð4], TBSTA[0

MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-7Part III. The Hardware Interface11.2 L2 Cache Interface ParametersThe L2 cache interface par

MOTOROLA Illustrations xxxixILLUSTRATIONSFigureNumberTitlePageNumber19-2 GSMR_HÑGeneral SCC Mode Register (High Order) ...

11-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interfacebus to the external L2 cache by asserting BG and DBG, respectively. I

MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-9Part III. The Hardware InterfaceFigure 11-4. Read Access with L2 CacheCLKBRBGAddrTSABBA0 &

11-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware Interface

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-1Chapter 12 IEEE 1149.1 Test Access Port120120The MPC8260 provides a dedicated user-accessibl

12-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 12-1. Test Logic Block DiagramThe TAP consists of the signals

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-3Part III. The Hardware InterfaceFigure 12-2. TAP Controller State Machine12.3 Boundary Scan

12-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart III. The Hardware InterfaceFigure 12-3. Output Pin Cell (O.Pin)Figure 12-4. Observe-Only Input P

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-5 Part III. The Hardware Interface Figure 12-5. Output Control Cell (IO.CTL)Figure 12-6. Gen

12-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface type. The third column lists the pin name for all pin-related cell

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-7 Part III. The Hardware Interface 35 IO.ctl g277.ctl Ñ Ñ36 i.obs pb[10] io Ñ37 o.pin pb[10]

OverviewPowerPC Processor CoreMemory MapSystem Interface Unit (SIU)ResetExternal Signals60x SignalsThe 60x BusClocks and Power ControlMemory Controll

xl MPC8260 PowerQUICC II UserÕs Manual MOTOROLAILLUSTRATIONSFigureNumberTitlePageNumber22-2 Control Character Table and RCCM ...

12-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 74 IO.ctl g263.ctl Ñ Ñ75 i.obs pb[13] io Ñ76 o.pin pb[13] io g262.

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-9 Part III. The Hardware Interface 113 IO.ctl g250.ctl Ñ Ñ114 i.obs pc[13] io Ñ115 o.pin pc[

12-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 152 IO.ctl g237.ctl Ñ Ñ153 i.obs pb[23] io Ñ154 o.pin pb[23] io g

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-11 Part III. The Hardware Interface 191 IO.ctl g224.ctl Ñ Ñ192 i.obs pb[20] io Ñ193 o.pin pb

12-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 230 IO.ctl g212.ctl Ñ Ñ231 i.obs pc[24] io Ñ232 o.pin pc[24] io g

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-13 Part III. The Hardware Interface 269 o.pin sreset_b io g170.ctl270 IO.ctl g170.ctl Ñ Ñ271

12-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 308 i.obs pa[30] io Ñ309 o.pin pa[30] io g154.ctl310 IO.ctl g154.

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-15 Part III. The Hardware Interface 347 IO.ctl g89.ctl Ñ Ñ348 i.obs psdval_b io Ñ349 o.pin p

12-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 386 IO.ctl g111.ctl Ñ Ñ387 i.obs a[26] io Ñ388 o.pin a[26] io g11

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-17 Part III. The Hardware Interface 425 i.obs a[8] io Ñ426 o.pin a[8] io g109.ctl427 i.obs a

MOTOROLA Illustrations xliILLUSTRATIONSFigureNumberTitlePageNumber26-19 SMC GCI Event Register (SMCE)/Mask Register (SMCM)...

12-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 464 i.obs bg_b io Ñ465 o.pin bg_b io g115.ctl466 IO.ctl g115.ctl

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-19 Part III. The Hardware Interface 503 i.obs d[54] io Ñ504 o.pin d[54] io g106.ctl505 i.obs

12-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 542 o.pin d[36] io g104.ctl543 i.obs d[28] io Ñ544 o.pin d[28] io

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-21 Part III. The Hardware Interface 581 o.pin d[18] io g102.ctl582 i.obs d[10] io Ñ583 o.pin

12-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 620 i.obs dp7_cse1_irq7_b io Ñ621 o.pin dp7_cse1_irq7_b io g99.ct

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-23 Part III. The Hardware Interface 659 o.pin we_dqm_bs_b[3] o Ñ660 o.pin we_dqm_bs_b[2] o Ñ

12-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 698 i.obs lcl_d_ad[4] io Ñ699 o.pin lcl_d_ad[4] io g40.ctl700 i.o

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-25 Part III. The Hardware Interface 737 IO.ctl g20.ctl Ñ Ñ738 i.obs lcl_dp_c_be[1] io Ñ739 o

12-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 776 o.pin lcl_d_ad[18] io g42.ctl777 i.obs lcl_d_ad[19] io Ñ778 o

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-27 Part III. The Hardware Interface 815 o.pin l_a25_gnt0_b io g31.ctl816 IO.ctl g31.ctl Ñ Ñ8

xlii MPC8260 PowerQUICC II UserÕs Manual MOTOROLAILLUSTRATIONSFigureNumberTitlePageNumber29-18 FMC, BRC Insertion...

12-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface 12.4 Instruction Register The MPC8260Õs JTAG implementation incl

MOTOROLA Chapter 12. IEEE 1149.1 Test Access Port 12-29 Part III. The Hardware Interface Table 12-3. Instruction Decoding CodeInstruction Descri

12-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III. The Hardware Interface The parallel output of the instruction register is set to all one

MOTOROLA Part IV. Communications Processor Module Part IV-i Part IV Communications Processor ModuleIntended AudiencePart IV is intended for syste

Part IV-ii MOTOROLAPart IV. Communications Processor Module¥ Chapter 19, ÒSerial Communications Controllers (SCCs),Ó describes the four serial communi

MOTOROLA Part IV. Communications Processor Module Part IV-iiiPart IV. Communications Processor Module¥ Chapter 33, ÒSerial Peripheral Interface (SP

Part IV-iv MOTOROLAPart IV. Communications Processor Module¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide (Motorola order #: MPCPRG

MOTOROLA Part IV. Communications Processor Module Part IV-vPart IV. Communications Processor ModuleTable vii. Acronyms and Abbreviated Terms Term M

Part IV-vi MOTOROLAPart IV. Communications Processor ModuleGUI Graphical user interfaceHDLC High-level data link controlI2C Inter-integrated circuit I

MOTOROLA Part IV. Communications Processor Module Part IV-viiPart IV. Communications Processor ModuleRT Real-timeRTOS Real-time operating systemRx

MOTOROLA Illustrations xliiiILLUSTRATIONSFigureNumberTitlePageNumber29-62 FCC Transmit Internal Rate Clocking...

Part IV-viii MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 13. Communications Processor Module Overview 13-1Chapter 13 Communications Processor Module Overview130130The MPC8260Õs communica

13-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module¥ Four full-duplex serial communications controllers (SCCs)

MOTOROLA Chapter 13. Communications Processor Module Overview 13-3Part IV. Communications Processor ModuleFigure 13-1. MPC8260 CPM Block Diagram13

13-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module13.3 Communications Processor (CP) The communications proce

MOTOROLA Chapter 13. Communications Processor Module Overview 13-5Part IV. Communications Processor ModuleFigure 13-2 shows the CP block diagram.

13-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module13.3.3 PowerPC Core InterfaceThe CP communicates with the P

MOTOROLA Chapter 13. Communications Processor Module Overview 13-7Part IV. Communications Processor Module13.3.5 Execution from RAMThe CP has an

13-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleRCCR bit Þelds are described in Table 13-3.Bits 0 1 2 3 4 5

MOTOROLA Chapter 13. Communications Processor Module Overview 13-9Part IV. Communications Processor Module13.3.7 RISC Time-Stamp Control Register

xliv MPC8260 PowerQUICC II UserÕs Manual MOTOROLAILLUSTRATIONSFigureNumberTitlePageNumber34-6 I2C Mode Register (I2MOD)...

13-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 13-4 describes RTSCR Þelds. 13.3.8 RISC Time-Stamp R

MOTOROLA Chapter 13. Communications Processor Module Overview 13-11Part IV. Communications Processor Module13.4 Command SetThe core issues comman

13-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module6Ð10 SBC Sub-block code. Set by the core to specify the sub

MOTOROLA Chapter 13. Communications Processor Module Overview 13-13Part IV. Communications Processor Module13.4.1.1 CP CommandsThe CP command opc

13-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe commands in Table 13-7 are described in Table 13-8. Tab

MOTOROLA Chapter 13. Communications Processor Module Overview 13-15Part IV. Communications Processor Module13.4.2 Command Register ExampleTo perf

13-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 13-8. Dual-Port RAM Memory MapThe dual-port RAM data

MOTOROLA Chapter 13. Communications Processor Module Overview 13-17Part IV. Communications Processor ModuleOnly the parameters in the parameter RA

13-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module13.6 RISC Timer TablesThe CP can control up to 16 software

MOTOROLA Chapter 13. Communications Processor Module Overview 13-19Part IV. Communications Processor Moduletimer tables. These timers are clocked

MOTOROLA Tables xlvTABLESTableNumberTitlePageNumberi Acronyms and Abbreviated Terms...

13-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe RISC timer table parameter RAM area begins at the RISC

MOTOROLA Chapter 13. Communications Processor Module Overview 13-21Part IV. Communications Processor ModuleTM_CMD Þelds are described in Figure 13

13-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module13.6.5 SET TIMER CommandThe SET TIMER command is used to e

MOTOROLA Chapter 13. Communications Processor Module Overview 13-23Part IV. Communications Processor Module3. (Optional) Write 0x0000 to the TM_CN

13-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module13.6.10 Using the RISC Timers to Track CP LoadingThe RISC

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-1Chapter 14 Serial Interface with Time-Slot Assigner140140Figure 14-1 shows a blo

14-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 14-1. SI Block DiagramIf the time-slot assigner (TSA)

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-3Part IV. Communications Processor Module14.1 FeaturesEach SI has the following

14-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module14.2 OverviewThe TSA implements both internal route selecti

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-5Part IV. Communications Processor ModuleFigure 14-2. Various Configurations of a

xlvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLATABLESTableNumberTitlePageNumber4-21 PISCR Field Descriptions...

14-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleAt its most ßexible, the TSA can provide four separate TDM c

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-7Part IV. Communications Processor Moduleassociated with the dual-port RAM. One S

14-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 14-4. Enabling Connections to the TSA14.4 Serial Int

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-9Part IV. Communications Processor Module14.4.1 One Multiplexed Channel with Sta

14-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV. Communications Processor Module Figure 14-6. One TDM Channel with Shadow RAM for Dynamic

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-11 Part IV. Communications Processor Module Table 14-1. SI x RAM Entry (MCC =

14-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV. Communications Processor Module Figure 14-8 shows how SWTR can be used. Figure 14-8. Us

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-13 Part IV. Communications Processor Module When MCC = 1, the SI x RAM entry Þ

14-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV. Communications Processor Module First, divide the frame from the start (the sync) to the

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-15 Part IV. Communications Processor Module ¥ Dynamic routing. A TDMÕs routing

MOTOROLA Tables xlviiTABLESTableNumberTitlePageNumber10-12 60x Bus-Assigned UPM Refresh Timer (PURT) ...

14-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV. Communications Processor Module Figure 14-9. Example: SI x RAM Dynamic Changes, TDMa an

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-17 Part IV. Communications Processor Module 14.5 Serial Interface Registers Th

14-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 14-5 describes SIxMR Þelds.Bits 0 1 2 3 4 5 6 7 8 9 1

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-19Part IV. Communications Processor Module6Ð7 RFSDx Receive frame sync delay for

14-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 14-12 shows the one-clock delay from sync to data wh

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-21Part IV. Communications Processor ModuleFigure 14-14 shows the effects of chang

14-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 14-16 shows the effects of changing FE when CE = 1 w

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-23Part IV. Communications Processor ModuleFigure 14-17 shows the effects of chang

14-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 14-6 describes SIxRSR Þelds. 14.5.4 SI Command Regis

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-25Part IV. Communications Processor ModuleTable 14-7 describes SIxCMDR Þelds.14.5

xlviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLATABLESTableNumberTitlePageNumber13-8 Command Descriptions ...

14-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleIn the basic rate of IDL, data on three channels (B1, B2, a

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-27Part IV. Communications Processor ModuleFigure 14-22. IDL Terminal AdaptorThe M

14-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe basic rate IDL bus has the three following channels:¥ B

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-29Part IV. Communications Processor Moduleof the D channel. If a collision is det

14-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFor example, based on the same 10-bit format as in Section

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-31Part IV. Communications Processor Module19. SI1CMDR is not used.20. SI1STR does

14-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 14-24. GCI Bus SignalsIn addition to the 144-Kbps IS

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-33Part IV. Communications Processor Module14.7.1 SI GCI Activation/Deactivation

14-34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFor example, assuming that SCC1 is connected to the D chann

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-35Part IV. Communications Processor Module14. Clear PSORB[17]. ConÞgures L1CLKO a

MOTOROLA Tables xlixTABLESTableNumberTitlePageNumber18-14 Parallel I/O Register ProgrammingÑPort D...

14-36 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 15. CPM Multiplexing 15-1Chapter 15 CPM Multiplexing150150The CPM multiplexing logic (CMX) connects the physical layerÑUTOPIA, MI

15-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 15-1. CPM Multiplexing Logic (CMX) Block Diagram15.1

MOTOROLA Chapter 15. CPM Multiplexing 15-3Part IV. Communications Processor ModuleThe multiple-PHY addressing selection supports the following opt

15-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 15-2. Enabling Connections to the TSA15.3 NMSI ConÞg

MOTOROLA Chapter 15. CPM Multiplexing 15-5Part IV. Communications Processor ModuleFigure 15-3. Bank of ClocksThe eight BRGs also make their clocks

15-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleNote that after a clock source is selected, the clock is giv

MOTOROLA Chapter 15. CPM Multiplexing 15-7Part IV. Communications Processor Module15.4.1 CMX UTOPIA Address Register (CMXUAR)The CMX UTOPIA addre

15-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleNote that each SADx and MADx corresponds to a pair of separa

MOTOROLA Chapter 15. CPM Multiplexing 15-9Part IV. Communications Processor ModuleFigure 15-6. Connection of the Slave AddressNote that the user m

MOTOROLA Contents v CONTENTS ParagraphNumberTitlePageNumber About This Book Before Using this ManualÑImportant Note...

l MPC8260 PowerQUICC II UserÕs Manual MOTOROLATABLESTableNumberTitlePageNumber22-8 Transmit Errors...

15-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 15-7. Multi-PHY Receive Address Multiplexing15.4.2

MOTOROLA Chapter 15. CPM Multiplexing 15-11Part IV. Communications Processor ModuleTable 15-3 describes CMXSI1CR Þelds.15.4.3 CMX SI2 Clock Route

15-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 15-4 describes CMXSI2CR Þelds.15.4.4 CMX FCC Clock R

MOTOROLA Chapter 15. CPM Multiplexing 15-13Part IV. Communications Processor ModuleTable 15-5 describes CMXFCR Þelds.Bits 0 1 2 3 4 5 6 7 8 9 10 1

15-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module15.4.5 CMX SCC Clock Route Register (CMXSCR)The CMX SCC cl

MOTOROLA Chapter 15. CPM Multiplexing 15-15Part IV. Communications Processor ModuleTable 15-6 describes CMXSCR Þelds.Bits 0 1 2 3 4 5 6 7 8 9 10 1

15-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module8 GR2 Grant support of SCC20 SCC2 transmitter does not supp

MOTOROLA Chapter 15. CPM Multiplexing 15-17Part IV. Communications Processor Module15.4.6 CMX SMC Clock Route Register (CMXSMR)The CMX SMC clock

15-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 15-7 describes CMXSMR Þelds.Bits 0 1 2 3 4 5 6 7Field

MOTOROLA Chapter 16. Baud-Rate Generators (BRGs) 16-1Chapter 16 Baud-Rate Generators (BRGs)160160The CPM contains eight independent, identical bau

MOTOROLA Tables liTABLESTableNumberTitlePageNumber26-17 SMC GCI Parameter RAM Memory Map...

16-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleEach BRG clock source can be BRGCLK, or a choice of two exte

MOTOROLA Chapter 16. Baud-Rate Generators (BRGs) 16-3Part IV. Communications Processor ModuleTable 16-1 describes the BRGCx Þelds. Table 16-2 show

16-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module16.2 Autobaud Operation on a UARTDuring the autobaud proces

MOTOROLA Chapter 16. Baud-Rate Generators (BRGs) 16-5Part IV. Communications Processor Module16.3 UART Baud Rate Examples For synchronous communi

16-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFor synchronous communication, the internal clock is identic

MOTOROLA Chapter 17. Timers 17-1Chapter 17 Timers170170The CPM includes four identical 16-bit general-purpose timers or two 32-bit timers. Eachgen

17-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module17.1 FeaturesThe key features of the timer include the foll

MOTOROLA Chapter 17. Timers 17-3Part IV. Communications Processor Moduleoutput can also be connected internally to the input of another timer, res

17-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 17-2. Timer Cascaded Mode Block DiagramIf TGCR[CAS] =

MOTOROLA Chapter 17. Timers 17-5Part IV. Communications Processor ModuleThe TGCR2 register is shown in Figure 17-4.Table 17-2 describes TGCR2 Þeld

lii MPC8260 PowerQUICC II UserÕs Manual MOTOROLATABLESTableNumberTitlePageNumber29-15 Receive and Transmit Connection Table Sizes ...

17-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module17.2.3 Timer Mode Registers (TMR1ÐTMR4)The four timer mode

MOTOROLA Chapter 17. Timers 17-7Part IV. Communications Processor Module17.2.4 Timer Reference Registers (TRR1ÐTRR4)Each timer reference register

17-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module17.2.5 Timer Capture Registers (TCR1ÐTCR4)Each timer captur

MOTOROLA Chapter 17. Timers 17-9Part IV. Communications Processor ModuleTable 17-4 describes TER Þelds.Table 17-4. TER Field DescriptionsBits Name

17-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-1Chapter 18 SDMA Channels and IDMA Emulation180180The MPC8260 has two physical serial DMA

18-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleOn a path 1 access, the SDMA channel must acquire the extern

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-3Part IV. Communications Processor ModuleFigure 18-2. SDMA Bus Arbitration (Transaction S

18-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module18.2.2 SDMA Mask Register (SDMR)The SDMA mask register (SDM

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-5Part IV. Communications Processor Module18.3 IDMA EmulationThe CPM can be conÞgured to

MOTOROLA Tables liiiTABLESTableNumberTitlePageNumber30-8 FPSMR Ethernet Field Descriptions ...

18-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModulePeripheral to/from memory features include the following:¥ E

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-7Part IV. Communications Processor ModuleFigure 18-5 shows the IDMA transfer buffer.Figur

18-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module¥ Last phase. The remaining data is read into the transfer b

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-9Part IV. Communications Processor ModuleBecause at least one of the transfer sizes (STS

18-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleData can be transferred between a peripheral and memory in

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-11Part IV. Communications Processor Moduleperipheral. When the transfer buffer has fewer

18-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module18.5.3 Controlling 60x Bus BandwidthSTS, DTS, and SS_MAX c

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-13Part IV. Communications Processor Moduleand DMA done (DONE[1Ð4]). DREQx may also be use

18-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Moduleignored until the request begins to be serviced. The servic

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-15Part IV. Communications Processor Moduleallocation and eliminates the need for core int

liv MPC8260 PowerQUICC II UserÕs Manual MOTOROLATABLESTableNumberTitlePageNumberA-3 Supervisor-Level PowerPC Registers (Non-SPR)...

18-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module18.8.2 IDMAx Parameter RAMWhen an IDMAx channel is conÞgur

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-17Part IV. Communications Processor Module0x0E STS Hword Source transfer size in bytes. A

18-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module18.8.2.1 DMA Channel Mode (DCM)The IDMA channel mode (DCM)

18-19 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module10 SINC Source increment address.0 Source address pointer (

18-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module18.8.2.2 Data Transfer Types as Programmed in DCMTable 18-

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-21Part IV. Communications Processor ModuleTable 18-7 describes valid STS/DTS values for m

18-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module18.8.3 IDMA PerformanceThe transfer parameters STS, DTS, S

18-23 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 18-9 describes IDSR/IDMR Þelds. 18.8.5 IDMA BDsSourc

18-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 18-10 describes IDMA BD Þelds.Table 18-10. IDMA BD Fi

18-25 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module11 DGBL Destination global0 Snooping is not activated.1 Sno

MOTOROLA About This Book lvAbout This BookThe primary objective of this manual is to help communications system designers buildsystems using the Motor

18-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module18.9 IDMA CommandsThe user has two commands to control eac

18-27 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleIn external request mode (ERM = 1), STOP_IDMA command proce

18-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module18.11 Programming the Parallel I/O RegistersThe parallel I

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-29Part IV. Communications Processor ModuleTable 18-14 describes parallel I/O register pro

18-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module18.12.2 Memory-to-Peripheral Fly-By Mode (Both on 60x Bus)

18-31 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleDCM[ERM] = 1 Transfers from peripheral are initiated by DRE

18-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-1Chapter 19 Serial Communications Controllers (SCCs)190190The MPC8260 has four se

19-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleAssociated with each SCC is a digital phase-locked loop (DPL

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-3Part IV. Communications Processor Module¥ DPLL circuitry for clock recovery with

lvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLAOrganizationFollowing is a summary and a brief description of the chapters of this manual:¥ Part I, ÒO

19-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 19-1 describes GSMR_H Þelds. Table 19-1. GSMR_H Field

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-5Part IV. Communications Processor Module25 TFL Transmit FIFO length.0 Normal ope

19-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 19-3 shows GSMR_L.Table 19-2 describes GSMR_L Þelds.B

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-7Part IV. Communications Processor Module7 TINV DPLL Tx input invert data. Must b

19-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module24Ð25 DIAG Diagnostic mode. 00 Normal operation, CTS and CD

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-9Part IV. Communications Processor Module19.1.2 Protocol-SpeciÞc Mode Register (

19-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe CP can be conÞgured to begin processing a new frame/buf

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-11Part IV. Communications Processor Module¥ The word at offset + 0x4 (buffer poin

19-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 19-7. SCC BD and Buffer Memory StructureIn all proto

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-13Part IV. Communications Processor Moduleset by the core (the buffer is empty).

MOTOROLA About This Book lviiÑ Chapter 13, ÒCommunications Processor Module Overview,Ó provides a brief overview of the MPC8260 CPM.Ñ Chapter 14, ÒSer

19-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module0x06 MRBLR Hword Maximum receive buffer length. DeÞnes the

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-15Part IV. Communications Processor Module19.3.1 SCC Base AddressesThe CPM maint

19-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 19-6 describes RFCRx/TFCRx Þelds. 19.3.3 Handling SC

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-17Part IV. Communications Processor ModuleFollow these steps to handle an SCC int

19-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module19.3.5 Controlling SCC Timing with RTS, CTS, and CDWhen GS

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-19Part IV. Communications Processor ModuleFigure 19-10. Output Delay from CTS Ass

19-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 19-11. CTS Lost in Synchronous ProtocolsNote that if

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-21Part IV. Communications Processor ModuleFigure 19-12. Using CD to Control Synch

19-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module19.3.6 Digital Phase-Locked Loop (DPLL) OperationEach SCC

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-23Part IV. Communications Processor ModuleFigure 19-14. DPLL Transmitter Block Di

lviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLAÑ Chapter 27, ÒMulti-Channel Controllers (MCCs),Ó describes the MPC8260Õs multi-channel controller (

19-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe DPLL can also be used to invert the data stream of a tr

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-25Part IV. Communications Processor ModuleFigure 19-15. DPLL Encoding ExamplesIf

19-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module19.3.7 Clock Glitch DetectionClock glitches cause problems

MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-27Part IV. Communications Processor Module4. If an INIT TX PARAMETERS command was

19-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 20. SCC UART Mode 20-1Chapter 20 SCC UART Mode200200The universal asynchronous receiver transmitter (UART) protocol is commonly u

20-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleAll standards provide handshaking signals, but some systems

MOTOROLA Chapter 20. SCC UART Mode 20-3Part IV. Communications Processor Module¥ Frame error, noise error, break, and idle detection¥ Transmit pre

20-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulereceive shift register are transferred to the receive FIFO b

MOTOROLA Chapter 20. SCC UART Mode 20-5Part IV. Communications Processor Module20.5 Data-Handling Methods: Character- or Message-BasedAn SCC UART

MOTOROLA About This Book lixSuggested ReadingThis section lists additional reading that provides background for the information in thismanual as well

20-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulehandling input data, a terminal driver may wait for an end-o

MOTOROLA Chapter 20. SCC UART Mode 20-7Part IV. Communications Processor ModuleReceive commands are described in Table 20-3. 20.8 Multidrop Syste

20-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 20-2. Two UART Multidrop Configurations20.9 Receivin

MOTOROLA Chapter 20. SCC UART Mode 20-9Part IV. Communications Processor ModuleTable 20-4 describes the data structure used in control character r

20-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module20.10 Hunt Mode (Receiver)A UART receiver in hunt mode rem

MOTOROLA Chapter 20. SCC UART Mode 20-11Part IV. Communications Processor Module20.12 Sending a Break (Transmitter)A break is an all-zeros charac

20-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 20-6 describes DSR Þelds.20.15 Handling Errors in th

MOTOROLA Chapter 20. SCC UART Mode 20-13Part IV. Communications Processor ModuleReception errors are described in Table 20-8. 20.16 UART Mode Reg

20-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 20-9 describes PSMR UART Þelds.Bit 0 1 2 3 4 5 6 7 8

MOTOROLA Chapter 20. SCC UART Mode 20-15Part IV. Communications Processor Module20.17 SCC UART Receive Buffer Descriptor (RxBD)The CPM uses RxBDs

vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS ParagraphNumberTitlePageNumber 1.7.2 Bus Configurations...

lx MPC8260 PowerQUICC II UserÕs Manual MOTOROLA¥ Application notesÑThese short documents contain useful information about speciÞc design issues useful

20-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module¥ An ENTER HUNT MODE or CLOSE RXBD command is issued.¥ An a

MOTOROLA Chapter 20. SCC UART Mode 20-17Part IV. Communications Processor ModuleFigure 20-8 shows the SCC UART RxBD. Table 20-10 describes RxBD st

20-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleSection 19.2, ÒSCC Buffer Descriptors (BDs),Ó describes the

MOTOROLA Chapter 20. SCC UART Mode 20-19Part IV. Communications Processor ModuleThe data length and buffer pointer Þelds are described in Section

20-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 20-10. SCC UART Interrupt Event ExampleSCCE bits are

MOTOROLA Chapter 20. SCC UART Mode 20-21Part IV. Communications Processor ModuleTable 20-12 describes SCCE Þelds for UART mode. 20.20 SCC UART St

20-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 20-13 describes UART SCCS Þelds.20.21 SCC UART Progr

MOTOROLA Chapter 20. SCC UART Mode 20-23Part IV. Communications Processor Module15. Write CHARACTER1Ð8 with 0x8000. They are not used.16. Write RC

20-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTo receive S-records, the core must wait for an RX interrup

MOTOROLA Chapter 21. SCC HDLC Mode 21-1Chapter 21 SCC HDLC Mode210210High-level data link control (HDLC) is one of the most common protocols in th

MOTOROLA About This Book lxiAcronyms and AbbreviationsTable i contains acronyms and abbreviations used in this document. Note that the meaningsfor som

21-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module21.1 SCC HDLC FeaturesThe main features of an SCC in HDLC m

MOTOROLA Chapter 21. SCC HDLC Mode 21-3Part IV. Communications Processor Moduleinsert a high-priority frame without aborting the current oneÑa gra

21-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module Table 21-1. HDLC-Specific SCC Parameter RAM Memory Map Offs

MOTOROLA Chapter 21. SCC HDLC Mode 21-5Part IV. Communications Processor ModuleFigure 21-2 shows 16- and 8-bit address recognition. Figure 21-2. H

21-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleReceive commands are described in Table 21-3.21.7 Handling

MOTOROLA Chapter 21. SCC HDLC Mode 21-7Part IV. Communications Processor Module21.8 HDLC Mode Register (PSMR)The protocol-speciÞc mode register (

21-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module21.9 SCC HDLC Receive Buffer Descriptor (RxBD)The CP uses t

MOTOROLA Chapter 21. SCC HDLC Mode 21-9Part IV. Communications Processor ModuleTable 21-7 describes HDLC RxBD status and control Þelds.Data length

21-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulelast buffer of a frame contains the total number of frame b

MOTOROLA Chapter 21. SCC HDLC Mode 21-11Part IV. Communications Processor Module21.10 SCC HDLC Transmit Buffer Descriptor (TxBD)The CP uses the T

lxii MPC8260 PowerQUICC II UserÕs Manual MOTOROLAFPU Floating-point unitGCI General circuit interface GPCM General-purpose chip-select machine GPR Gen

21-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe data length and buffer pointer Þelds are described in S

MOTOROLA Chapter 21. SCC HDLC Mode 21-13Part IV. Communications Processor ModuleFigure 21-8 shows interrupts that can be generated using the HDLC

21-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module21.12 SCC HDLC Status Register (SCCS)The SCC status regist

MOTOROLA Chapter 21. SCC HDLC Mode 21-15Part IV. Communications Processor Module21.13.1 SCC HDLC Programming Example #1The following initializati

21-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module19. Initialize the TxBD. Assume the Tx data frame is at 0x0

MOTOROLA Chapter 21. SCC HDLC Mode 21-17Part IV. Communications Processor Module21.14 HDLC Bus Mode with Collision DetectionThe HDLC controller i

21-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 21-10 shows the most common HDLC bus LAN conÞguratio

MOTOROLA Chapter 21. SCC HDLC Mode 21-19Part IV. Communications Processor ModuleFigure 21-11. Typical HDLC Bus Single-Master Configuration21.14.1

21-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Moduletransmission stops after that bit and waits for an idle lin

MOTOROLA Chapter 21. SCC HDLC Mode 21-21Part IV. Communications Processor ModuleFigure 21-13. Nonsymmetrical Tx Clock Duty Cycle for Increased Per

MOTOROLA About This Book lxiiiPCI Peripheral component interconnectPCMCIA Personal Computer Memory Card International AssociationPIR Processor identiÞ

21-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 21-15. Delayed RTS Mode21.14.5 Using the Time-Slot

MOTOROLA Chapter 21. SCC HDLC Mode 21-23Part IV. Communications Processor Module21.14.6 HDLC Bus Protocol ProgrammingThe HDLC bus on the MPC8260

21-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 22. SCC BISYNC Mode 22-1Chapter 22 SCC BISYNC Mode220220The byte-oriented BISYNC protocol was developed by IBM for use in network

22-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Moduletransmission, an underrun must not occur between the DLE and

MOTOROLA Chapter 22. SCC BISYNC Mode 22-3Part IV. Communications Processor ModuleIf no additional buffers have been sent to the controller for tra

22-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleGSMR[MODE] determines the protocol for each SCC. The SYN1ÐSY

MOTOROLA Chapter 22. SCC BISYNC Mode 22-5Part IV. Communications Processor Module22.5 SCC BISYNC CommandsTransmit and receive commands are issued

22-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module22.6 SCC BISYNC Control Character RecognitionThe BISYNC con

MOTOROLA Chapter 22. SCC BISYNC Mode 22-7Part IV. Communications Processor ModuleTable 22-4 describes control character table and RCCM Þelds.22.7

lxiv MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPowerPC Architecture Terminology ConventionsTable ii lists certain terms used in this manual that dif

22-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 22-5 describes BSYNC Þelds. 22.8 SCC BISYNC DLE Regis

MOTOROLA Chapter 22. SCC BISYNC Mode 22-9Part IV. Communications Processor ModuleTable 22-6 describes BDLE Þelds. 22.9 Sending and Receiving the

22-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 22-8 describes transmit errors.Table 22-9 describes r

MOTOROLA Chapter 22. SCC BISYNC Mode 22-11Part IV. Communications Processor ModuleTable 22-10 describes PSMR Þelds.Table 22-10. PSMR Field Descrip

22-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module22.12 SCC BISYNC Receive BD (RxBD)The CP uses BDs to repor

MOTOROLA Chapter 22. SCC BISYNC Mode 22-13Part IV. Communications Processor ModuleData length and buffer pointer Þelds are described in Section 19

22-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module22.13 SCC BISYNC Transmit BD (TxBD)The CP arranges data to

MOTOROLA Chapter 22. SCC BISYNC Mode 22-15Part IV. Communications Processor ModuleData length and buffer pointer Þelds are described in Section 19

22-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 22-13 describes SCCE and SCCM Þelds. 22.15 SCC Statu

MOTOROLA Chapter 22. SCC BISYNC Mode 22-17Part IV. Communications Processor ModuleTable 22-14 describes SCCS Þelds. 22.16 Programming the SCC BIS

MOTOROLA About This Book lxvTable iii describes instruction Þeld notation conventions used in this manual. Table iii. Instruction Field Conventions Th

22-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleAfter ETX, a BCS is expected; then the buffer should be clo

MOTOROLA Chapter 22. SCC BISYNC Mode 22-19Part IV. Communications Processor Module13. Write BSYNC with 0x8033, assuming a SYNC value of 0x33.14. W

22-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 23. SCC Transparent Mode 23-1Chapter 23 SCC Transparent Mode230230Transparent mode (also called totally transparent or promiscuou

23-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module¥ Another protocol can be performed on the other half of the

MOTOROLA Chapter 23. SCC Transparent Mode 23-3Part IV. Communications Processor ModuleAfter a buffer is full, the SCC clears RxBD[E] and generates

23-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleNote that the transparent controller does not automatically

MOTOROLA Chapter 23. SCC Transparent Mode 23-5Part IV. Communications Processor ModuleFigure 23-1. Sending Transparent Frames between MPC8260sMPC8

23-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleNote that when using the TSA, a newly-enabled transmitter se

MOTOROLA Chapter 23. SCC Transparent Mode 23-7Part IV. Communications Processor ModuleCRC_P and CRC_C overlap with the CRC parameters for the HDLC

lxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA

23-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 23-4 describes receive commands.23.8 Handling Errors

MOTOROLA Chapter 23. SCC Transparent Mode 23-9Part IV. Communications Processor Module23.9 Transparent Mode and the PSMRThe protocol-speciÞc mode

23-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleData length and buffer pointer Þelds are described in Secti

MOTOROLA Chapter 23. SCC Transparent Mode 23-11Part IV. Communications Processor ModuleTable 23-8 describes SCC Transparent TxBD status and contro

23-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleData length and buffer pointer Þelds are described in Secti

MOTOROLA Chapter 23. SCC Transparent Mode 23-13Part IV. Communications Processor Module23.13 SCC Status Register in Transparent Mode (SCCS)The SC

23-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module1. ConÞgure port D pins to enable TXD2 and RXD2. Set PPARD[

MOTOROLA Chapter 23. SCC Transparent Mode 23-15Part IV. Communications Processor ModuleNote that after 5 bytes are sent, the Tx buffer is closed a

23-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 24. SCC Ethernet Mode 24-1Chapter 24 SCC Ethernet Mode240240The Ethernet IEEE 802.3 protocol is a widely used LAN protocol based

MOTOROLA Part I. Overview Part I-lxviiPart IOverviewIntended AudiencePart I is intended for readers who need a high-level understanding of the MP

24-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulea random period of time, called a backoff, before trying to

MOTOROLA Chapter 24. SCC Ethernet Mode 24-3Part IV. Communications Processor Module24.2 FeaturesThe following list summarizes the main features o

24-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleÑ Number of retries per frameÑ Deferred frame indicationÑ La

MOTOROLA Chapter 24. SCC Ethernet Mode 24-5Part IV. Communications Processor ModuleFigure 24-3. Connecting the MPC8260 to EthernetThe EEST has sim

24-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe Ethernet controller stores the Þrst 5 to 8 bytes of the

MOTOROLA Chapter 24. SCC Ethernet Mode 24-7Part IV. Communications Processor Moduleaddress recognition on the frame. The receiver can receive phys

24-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module24.7 SCC Ethernet Parameter RAMFor Ethernet mode, the proto

MOTOROLA Chapter 24. SCC Ethernet Mode 24-9Part IV. Communications Processor Module0x54 MAX_B Hword Maximum BD byte count. 0x58 GADDR1 Hword Group

24-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module24.8 Programming the Ethernet ControllerThe core conÞgures

MOTOROLA Chapter 24. SCC Ethernet Mode 24-11Part IV. Communications Processor ModuleTable 24-3 describes receive commands. Note that after a CPM r

Part I-lxviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewREG[FIELD] Abbreviations or acronyms for registers or buffer descriptors are

24-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 24-4. Ethernet Address Recognition FlowchartIn group

MOTOROLA Chapter 24. SCC Ethernet Mode 24-13Part IV. Communications Processor ModuleIf the external CAM stores addresses that should be rejected r

24-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleIf a collision occurs while a frame is being received, rece

MOTOROLA Chapter 24. SCC Ethernet Mode 24-15Part IV. Communications Processor ModuleTable 24-4 describes reception errors. 24.17 Ethernet Mode Re

24-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 24-6 describes PSMR Þelds.Table 24-6. PSMR Field Desc

MOTOROLA Chapter 24. SCC Ethernet Mode 24-17Part IV. Communications Processor Module24.18 SCC Ethernet Receive BDThe Ethernet controller uses the

24-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleData length and buffer pointer Þelds are described in Secti

MOTOROLA Chapter 24. SCC Ethernet Mode 24-19Part IV. Communications Processor ModuleFigure 24-7. Ethernet Receiving using RxBDs24.19 SCC Ethernet

24-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleconÞrm transmission or indicate errors so the core knows bu

MOTOROLA Chapter 24. SCC Ethernet Mode 24-21Part IV. Communications Processor ModuleData length and buffer pointer Þelds are described in Section

MOTOROLA Part I. Overview Part I-lxixPart I. OverviewISDN Integrated services digital networkITLB Instruction translation lookaside bufferIU Inte

24-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 24-10 shows an example of interrupts that can be gen

MOTOROLA Chapter 24. SCC Ethernet Mode 24-23Part IV. Communications Processor ModuleNote that the SCC status register (SCCS) cannot be used with t

24-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module20. Initialize the TxBD and assume the Tx data frame is at

MOTOROLA Chapter 25. SCC AppleTalk Mode 25-1Chapter 25 SCC AppleTalk Mode250250AppleTalk is a set of protocols developed by Apple Computer, Inc. t

25-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe control byte within the LocalTalk frame indicates the ty

MOTOROLA Chapter 25. SCC AppleTalk Mode 25-3Part IV. Communications Processor Module25.3 Connecting to AppleTalkAs shown in Figure , the MPC8260

25-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module5. Clear TEND for default operation.6. Set TPP to 0b11 for a

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-1Chapter 26 Serial Management Controllers (SMCs)260260The two serial management contr

26-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 26-1. SMC Block DiagramThe receive data source can be

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-3Part IV. Communications Processor Module¥ Full-duplex operation¥ Local loopback and

MOTOROLA Contents vii CONTENTS ParagraphNumberTitlePageNumber 2.5.1 PowerPC Exception Model ...

Part I-lxx MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewTx TransmitUART Universal asynchronous receiver/transmitterUISA User instructio

26-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 26-1 describes SMCMR Þelds.Table 26-1. SMCMR1/SMCMR2 F

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-5Part IV. Communications Processor Module26.2.2 SMC Buffer Descriptor OperationIn UA

26-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe BD table allows buffers to be deÞned for transmission an

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-7Part IV. Communications Processor ModuleTo extract data from a partially full receiv

26-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleCertain parameter RAM values must be initialized before the

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-9Part IV. Communications Processor Module26.2.4 Disabling SMCs On-the-FlyAn SMC can

26-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module26.2.4.4 SMC Receiver Shortcut SequenceThis shorter sequen

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-11Part IV. Communications Processor ModuleHowever, SMCs allow a data length of up to

26-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module26.3.3 SMC UART Channel Reception ProcessWhen the core ena

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-13Part IV. Communications Processor ModuleTable 26-5 describes receive commands issue

MOTOROLA Chapter 1. Overview 1-1Chapter 1 Overview1010The MPC8260 PowerQUICC IIª is a versatile communications processor that integrateson one ch

26-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module26.3.9 SMC UART RxBDUsing the BDs, the CP reports informat

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-15Part IV. Communications Processor ModuleData length represents the number of octets

26-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 26-7. RxBD Example26.3.10 SMC UART TxBDData is sent

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-17Part IV. Communications Processor ModuleTable 26-8 describes SMC UART TxBD Þelds. D

26-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulemust be even. For instance, the pointer to 8-bit data, 1 st

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-19Part IV. Communications Processor ModuleFigure 26-10. SMC UART Interrupts Example26

26-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module9. Write MAX_IDL with 0x0000 in the SMC UART-speciÞc parame

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-21Part IV. Communications Processor ModuleHowever, the SMC in transparent mode provid

26-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module26.4.3 SMC Transparent Channel Reception ProcessWhen the c

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-23Part IV. Communications Processor ModuleFigure 26-11. Synchronization with SMSYNxIf

1-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewÑ PowerPC architecture-compliant memory management unit (MMU)Ñ Common on-chip processo

26-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 26-12. Synchronization with the TSAOnce SMCMR[REN] i

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-25Part IV. Communications Processor Modulealways ready and that underruns do not occu

26-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module26.4.8 SMC Transparent RxBDUsing BDs, the CP reports infor

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-27Part IV. Communications Processor ModuleData length and buffer pointer Þelds are de

26-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleData length represents the number of octets the CP should t

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-29Part IV. Communications Processor Module26.4.11 SMC Transparent NMSI Programming E

26-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module26.5 The SMC in GCI ModeThe SMC can control the C/I and mo

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-31Part IV. Communications Processor Module26.5.2 Handling the GCI Monitor ChannelThe

26-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module26.5.4 SMC GCI CommandsThe commands in Table 26-18 are iss

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-33Part IV. Communications Processor ModuleTable 26-20 describes SMC monitor channel T

MOTOROLA Chapter 1. Overview 1-3Part I. OverviewÑ Byte write enables and selectable parity generationÑ 32-bit address decodes with programmable ba

26-34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 26-22 describes SMC C/I channel TxBD Þelds. 26.5.9 S

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-1Chapter 27 Multi-Channel Controllers (MCCs)270270The MPC8260Õs two multi-channel control

27-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module27.2 MCC Data Structure OrganizationEach MCC uses the follo

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-3Part IV. Communications Processor ModuleFigure 27-1. BD Structure for One MCC27.3 Globa

27-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module0x0C RINTTMP Word Temporary location for holding the receive

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-5Part IV. Communications Processor Module27.4 Channel Extra ParametersTable 27-2 describ

27-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulechannels which uses the slot synchronization. Figure 27-5 sh

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-7Part IV. Communications Processor ModuleFigure 27-4. Receiver Super Channel with Slot Sy

27-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module27.6 Channel-SpeciÞc HDLC ParametersTable 27-3 describes ch

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-9Part IV. Communications Processor Module27.6.1 Internal Transmitter State (TSTATE)Inter

1-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewÑ Two serial management controllers (SMCs), identical to those of the MPC860Ð Provide

27-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTo enable an interrupt, set the corresponding bit. If a bit

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-11Part IV. Communications Processor Module27.6.4 Internal Receiver State (RSTATE)Interna

27-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleRSTATE high-byte Þelds are described in Table 27-6. 27.7 C

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-13Part IV. Communications Processor Module27.7.1 Channel Mode Register (CHAMR)ÑTranspare

27-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleCHAMR Þelds are described in Table 27-5, Bits 0 1 2 3 4 5 6

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-15Part IV. Communications Processor Module27.8 MCC ConÞguration Registers (MCCFx)The MCC

27-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleNote that the TDM group channel assignments made in MCCF mu

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-17Part IV. Communications Processor ModuleTable 27-12 describes receive commands. 27.10

27-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Moduleend of the table). When an MCC channel generates an interru

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-19Part IV. Communications Processor ModuleTable 27-13 describes MCCE Þelds. 27.10.1.1 In

MOTOROLA Chapter 1. Overview 1-5Part I. OverviewFigure 1-1. MPC8260 Block DiagramBoth the system core and the CPM have an internal PLL, which allo

27-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 27-14 describes interrupt circular table Þelds. Bits

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-21Part IV. Communications Processor Module27.11 MCC Buffer DescriptorsEach MCC channel r

27-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module5 F First in frame. The HDLC controller sets F = 1 for the

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-23Part IV. Communications Processor ModuleThe data length and buffer pointer are describe

27-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe data length and buffer pointer are described below:¥ Da

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-25Part IV. Communications Processor Module27.12.1 Single-Channel InitializationThe follo

27-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module27.12.2 Super Channel InitializationThe following steps in

MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-27Part IV. Communications Processor ModuleIf multiple synchronized channels are used (as

27-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-1Chapter 28 Fast Communications Controllers (FCCs)280280The MPC8260Õs fast communic

1-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewThe MPC603e core has an internal common on-chip (COP) debug processor. Thisprocessor a

28-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module28.1 OverviewMPC8260 FCCs can be conÞgured independently to

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-3Part IV. Communications Processor ModuleFigure 28-1. FCC Block Diagram28.2 Genera

28-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 28-1 describes GFMR Þelds. Table 28-1. GFMR Register F

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-5Part IV. Communications Processor Module5 CDP CD pulse (transparent mode only)0 No

28-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module22Ð23 TENC Transmitter encoding method. The user should set

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-7Part IV. Communications Processor Module28.3 FCC Protocol-SpeciÞc Mode Registers

28-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFields in the TODR are described in Table 28-428.6 FCC Buff

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-9Part IV. Communications Processor ModuleFigure 28-3. FCC Memory StructureThe forma

28-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe BDs and data buffers can be anywhere in the system memo

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-11Part IV. Communications Processor ModuleSome parameter RAM values must be initial

MOTOROLA Chapter 1. Overview 1-7Part I. OverviewThe following list summarizes the major features of the CPM:¥ The CP is an embedded 32-bit RISC co

28-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module0x0C RBASE Word RxBD base address (must be divisible by eig

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-13Part IV. Communications Processor Module28.7.1 FCC Function Code Registers (FCRx

28-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleEvents that can cause the FCC to interrupt the processor va

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-15Part IV. Communications Processor Module6. Write the FDSR.7. Initialize the requi

28-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleRTS is asserted when FCC has data to transmit in the transm

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-17Part IV. Communications Processor ModuleFigure 28-7. Output Delay from CTS Assert

28-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 28-8. CTS LostNote that if GFMR[CTSS] = 1, all CTS t

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-19Part IV. Communications Processor ModuleFigure 28-9. Using CD to Control Receptio

28-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module28.12.1 FCC Transmitter Full SequenceFor the FCC transmitt

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-21Part IV. Communications Processor Module28.12.4 FCC Receiver Shortcut SequenceA

1-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewNOTEA bar over a signal name indicates that the signal is activelowÑfor example, BB (b

28-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 29. ATM Controller 29-1Chapter 29 ATM Controller290290The ATM controller provides the ATM and AAL layers of the ATM protocol usi

MOTOROLA Chapter 29. ATM Controller 29-2Part IV. Communications Processor Module29.1 FeaturesThe ATM controller has the following features:¥ Ful

29-3 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleÐ Sequence number checkÐ Sequence number protection (CRC-3 a

MOTOROLA Chapter 29. ATM Controller 29-4Part IV. Communications Processor Module¥ Available bit rate (ABR)Ñ Performs ATMF UNI 4.0 ABR ßow control

29-5 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.2.1 Transmitter OverviewBefore the transmitter is enable

29-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulegenerated and inserted into the cell. The MPC8260 supports s

29-7 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleReception starts when the PHY asserts the receive cell avail

29-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleÞrst byte of the new buffer. If an SN mismatch is detected,

29-9 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFor information about cell rate pacing, see Section 29.3.5,

MOTOROLA Chapter 1. Overview 1-9Part I. Overview1.4 Differences between MPC860 and MPC8260 The following MPC860 features are not included in the

29-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-1. APC Scheduling Table MechanismEach 2-byte time

29-11 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.3.3.2 Determining the Number of Slots in a Scheduling T

29-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe resulting number of slots is written into TCT[PCR] and

29-13 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleEquation D yields the number of slots the user writes to th

29-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.4 VCI/VPI Address Lookup MechanismThe MPC8260 supports

29-15 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe external CAM Þelds are described in Table 29-229.4.2 A

29-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-5. Address Compression MechanismFigure 29-5 shows

29-17 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.4.2.1 VP-Level Address Compression Table (VPLT)The size

29-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-7 shows the VP pointer address compression from T

29-19 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.4.4 Receive Raw Cell QueueChannel one in the RCT is res

viii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS ParagraphNumberTitlePageNumber 4.3.2.2 60x Bus Arbiter Configuration Register (PPC_ACR) ..

1-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview1.6 MPC8260 ConÞgurationsThe MPC8260 offers ßexibility in conÞguring the device for

29-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.5 Available Bit Rate (ABR) Flow ControlWhile CBR servic

29-21 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe MPC8260 ABR ßow control implements both source and dest

29-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module3. The CCR and MCR Þelds are taken from the F-RM and is not

29-23 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-12. ABR Transmit Flow (Continued) RM/DATA In Rate

29-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-13. ABR Transmit Flow (Continued)B-RM/DATA In Rat

29-25 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-14. ABR Receive Flow 29.5.2 RM Cell StructureTab

29-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.5.2.1 RM Cell Rate RepresentationRates in the RM cells

29-27 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.5.3 ABR Flow Control SetupFollow these steps to setup A

29-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-9 lists pre-assigned header values at the network-

29-29 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.6.5 Transmitting OAM F4 or F5 CellsOAM F4/F5 ßow cells

MOTOROLA Chapter 1. Overview 1-11Part I. OverviewFCCs can also be used to run slower HDLC or 10 BaseT, for example. The CPÕs RISCarchitecture has

29-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-10 describes performance monitoring cell Þelds. 29

29-31 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleBEDC is calculated. When an FMC is received, the CP adds th

29-32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-18. FMC, BRC Insertion29.6.6.4 BRC Performance C

29-33 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFor AAL5 and AAL1 the extra header is taken from the Rx and

29-34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleCounters are implemented in the dual-port RAM for each PHY

29-35 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-21. ATM-to-TDM Interworking When going from TDM t

29-36 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulecope with the ATM networkÕs CDV), set ATM RxBD[I]. When the

29-37 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulecore then moves the buffer pointer to the MCC. The bufferÕs

29-38 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-11. ATM Parameter RAM Map Offset1Name Width Descri

29-39 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module0x6C BD_BASE_EXT Word BD table base address extension. BD_B

1-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewIn this application, eight TDM ports are connected to external framers. In the MPC826

29-40 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only)The UEAD

29-41 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.1.3 Global Mode Entry (GMODE)Figure 29-23 shows the

29-42 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Moduleuse ABR, VBR or UBR+ services. Each connection table entry

29-43 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-24. Example of a 1024-Entry Receive Connection Ta

29-44 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15Offset + 0x00 Ñ GBL BO

29-45 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-16 describes RCT Þelds.Table 29-16. RCT Field Desc

29-46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.2.2.1 AAL5 Protocol-SpeciÞc RCTFigure 29-26 shows th

29-47 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-17 describes AAL5 protocol speciÞc RCT Þelds. 29.1

29-48 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-18 describes AAL5-ABR protocol-speciÞc RCT Þelds.2

29-49 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-19. AAL1 Protocol-Specific RCT Field Descriptions

MOTOROLA Chapter 1. Overview 1-13Part I. OverviewIn this application, the MPC8260 is connected to four TDM interfaces channalizing up to128 channe

29-50 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.2.2.4 AAL0 Protocol-SpeciÞc RCT Figure 29-29 shows t

29-51 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.2.3 Transmit Connection Table (TCT)Figure 29-30 show

29-52 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-21. TCT Field Descriptions Offset Bits Name Descri

29-53 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module0x02 0 Ñ Internal use only. Initialize to 0. 1 INF Used for

29-54 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.2.3.1 AAL5 Protocol-SpeciÞc TCTFigure 29-31 shows th

29-55 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-23 describes AAL1 protocol-speciÞc TCT Þelds.29.10

29-56 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-24 describes AAL0 protocol-speciÞc TCT Þelds.29.10

29-57 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.2.3.5 UBR+ Protocol-SpeciÞc TCTEFigure 29-35 shows t

29-58 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.2.3.6 ABR Protocol-SpeciÞc TCTEFigure 29-36 shows th

29-59 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module4Ð6 Ñ Reserved, should be cleared.7 CP-TA Cell loss priorit

1-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview1.7.1.4 Cellular Base StationFigure 1-6 shows a cellular base station conÞguration.F

29-60 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.3 OAM Performance Monitoring TablesThe OAM performan

29-61 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.4 APC Data StructureThe APC data structure consists

29-62 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-38. ATM Pace Control Data Structure 29.10.4.1 AP

29-63 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.4.2 APC Priority TableEach PHYÕs APC priority table

29-64 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-31 describes control slot Þelds. 29.10.5 ATM Cont

29-65 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module Figure 29-41. Transmit Buffers and BD Table Example29.10.5

29-66 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module Figure 29-42. Receive Static Buffer Allocation Example29.1

29-67 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module Figure 29-43. Receive Global Buffer Allocation Example29.1

29-68 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-32 describes free buffer pool entry Þelds.29.10.5.

29-69 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.5.3 ATM Controller BuffersTable 29-34 describes prop

MOTOROLA Chapter 1. Overview 1-15Part I. OverviewThe MPC8260 CPM supports a total aggregate throughput of 710 Mbps at 133 MHz. Thisincludes two fu

29-70 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-35 describes AAL5 RxBD Þelds. Table 29-35. AAL5 Rx

29-71 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.5.5 AAL1 RxBDFigure 29-47 shows the AAL1 RxBD. 0x02

29-72 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-36 describes AAL1 RxBD Þelds.29.10.5.6 AAL0 RxBDF

29-73 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-37 describes AAL0 RxBD Þelds.29.10.5.7 AAL5, AAL1

29-74 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.5.8 AAL5 TxBDsFigure 29-50 shows the AAL5 TxBD.Offse

29-75 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-38 describes AAL5 TxBD Þelds.Table 29-38. AAL5 TxB

29-76 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.5.9 AAL1 TxBDsFigure 29-51 shows the AAL1 TxBD. Tabl

29-77 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.5.10 AAL0 TxBDsFigure 29-52 shows AAL0 TxBDs. Note t

29-78 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.10.5.11 AAL5, AAL1 User-DeÞned CellÑTxBD ExtensionIn us

29-79 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.11 ATM ExceptionsThe ATM controller interrupt handling

1-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overviewnot need to be heavily processed by the core. The CP can store large data frames in t

29-80 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module Figure 29-55. Interrupt Queue Structure29.11.2 Interrupt

29-81 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-42 describes interrupt queue entry Þelds. 29.11.3

29-82 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.12 The UTOPIA InterfaceThe ATM controller interfaces wi

29-83 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.12.1.1 UTOPIA Master Multiple PHY OperationThe cell tra

29-84 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-45 describes UTOPIA slave mode signals.29.12.2.1

29-85 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.12.2.3 UTOPIA Loop-Back ModesThe UTOPIA interface suppo

29-86 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-47 describes FPSMR Þelds.Bits 0 1 2 3 4 5 6 7 8 9

29-87 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module29.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)The

29-88 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 29-48 describes FCCE Þelds.29.13.4 FCC Transmit Inte

MOTOROLA Chapter 29. ATM Controller 29-89Part IV. Communications Processor ModuleTable 29-49 describes FTIRRx Þelds. Figure 29-62 shows how trans

MOTOROLA Chapter 1. Overview 1-17Part I. OverviewSerial throughput is enhanced by connecting one MPC8260 in master or slave mode (withsystem core

29-90 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleSee also Section 29.16.1, ÒUsing Transmit Internal Rate Mod

MOTOROLA Chapter 29. ATM Controller 29-91Part IV. Communications Processor Module29.15 SRTS Generation and Clock Recovery Using External LogicTh

29-92 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 29-65. AAL1 SRTS Clock Recovery Using External Logic

MOTOROLA Chapter 29. ATM Controller 29-93Part IV. Communications Processor ModuleFor example, suppose a system uses a 155.52-Mbps OC-3 device as

29-94 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 30. Fast Ethernet Controller 30-1Chapter 30 Fast Ethernet Controller300300The Ethernet IEEE 802.3 protocol is a widely-used LAN b

30-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Moduleon the LAN. If a collision is detected, the station forces a

MOTOROLA Chapter 30. Fast Ethernet Controller 30-3Part IV. Communications Processor ModuleFigure 30-2. Ethernet Block Diagram 30.2 FeaturesThe fo

30-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module¥ Multibuffer data structure¥ Supports 48-bit addresses in t

MOTOROLA Chapter 30. Fast Ethernet Controller 30-5Part IV. Communications Processor ModuleFigure 30-3. Connecting the MPC8260 to EthernetEach FCC

1-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview

30-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Moduleframe delimiter, and frame information are sent in that orde

MOTOROLA Chapter 30. Fast Ethernet Controller 30-7Part IV. Communications Processor Module30.5 Ethernet Channel Frame ReceptionThe Ethernet recei

30-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleEthernet controller then waits for a new frame. The Ethernet

MOTOROLA Chapter 30. Fast Ethernet Controller 30-9Part IV. Communications Processor Module30.8 Ethernet Parameter RAMFor Ethernet mode, the proto

30-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module0x72 PADDR1_H Hword The 48-bit individual address of this s

MOTOROLA Chapter 30. Fast Ethernet Controller 30-11Part IV. Communications Processor Module0xBA MAXD2 Hword Max DMA2 length register (typically 15

30-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module30.9 Programming ModelThe core conÞgures an FCC to operate

MOTOROLA Chapter 30. Fast Ethernet Controller 30-13Part IV. Communications Processor ModuleReceive commands that apply to Ethernet are described i

30-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module30.11 RMON SupportThe Fast Ethernet controller can automat

MOTOROLA Chapter 30. Fast Ethernet Controller 30-15Part IV. Communications Processor Module30.12 Ethernet Address RecognitionThe Ethernet control

MOTOROLA Chapter 2. PowerPC Processor Core 2-1Chapter 2 PowerPC Processor Core2020The MPC8260 contains an embedded version of the PowerPC 603eª pr

30-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 30-4. Ethernet Address Recognition FlowchartCheckAdd

MOTOROLA Chapter 30. Fast Ethernet Controller 30-17Part IV. Communications Processor ModuleIn the physical type of address recognition, the Ethern

30-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleNOTEThe hash tables cannot be used to reject frames that ma

MOTOROLA Chapter 30. Fast Ethernet Controller 30-19Part IV. Communications Processor Module30.17 Ethernet Error-Handling ProcedureThe Ethernet co

30-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module30.18.1 FCC Ethernet Mode Register (FPSMR)In Ethernet mode

MOTOROLA Chapter 30. Fast Ethernet Controller 30-21Part IV. Communications Processor Module30.18.2 Ethernet Event Register (FCCE)/Mask Register (

30-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Moduleaffect bit values. Unmasked FCCE bits must be cleared befor

MOTOROLA Chapter 30. Fast Ethernet Controller 30-23Part IV. Communications Processor ModuleFigure 30-7. Ethernet Interrupt Events ExampleNote that

30-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 30-10 describes Ethernet RxBD Þelds.0 1 2 3 4 5 6 7 8

MOTOROLA Chapter 30. Fast Ethernet Controller 30-25Part IV. Communications Processor ModuleData length is the number of octets the CP writes into

MOTOROLA Contents ix CONTENTS ParagraphNumberTitlePageNumber External Signals 6.1 Functional Pinout ...

2-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. OverviewFigure 2-1. MPC8260 Integrated Processor Core Block DiagramThe processor core is a sup

30-26 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 30-9. Ethernet Receiving Using RxBDs30.20 Ethernet

MOTOROLA Chapter 30. Fast Ethernet Controller 30-27Part IV. Communications Processor ModuleTable 30-11 describes Ethernet TxBD Þelds.0 1 2 3 4 5 6

30-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleData length is the number of octets the Ethernet controller

MOTOROLA Chapter 31. FCC HDLC Controller 31-1Chapter 31 FCC HDLC Controller310310Layer 2 of the seven-layer OSI model is the data link layer (DLL)

31-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module31.1 Key FeaturesKey features of the HDLC include the follo

MOTOROLA Chapter 31. FCC HDLC Controller 31-3Part IV. Communications Processor ModuleTo rearrange the transmit queue before the CP has sent all bu

31-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module31.4 HDLC Parameter RAMWhen an FCC operates in HDLC mode, t

MOTOROLA Chapter 31. FCC HDLC Controller 31-5Part IV. Communications Processor ModuleFigure 31-2 shows an example of using HMASK and HADDR[1Ð4]. F

31-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 31-3 describes the receive commands that apply to the

MOTOROLA Chapter 31. FCC HDLC Controller 31-7Part IV. Communications Processor ModuleTable 31-5 describes HDLC reception errors, which are reporte

MOTOROLA Chapter 2. PowerPC Processor Core 2-3Part I. OverviewThe processor core integrates four execution unitsÑan integer unit (IU), a branchproc

31-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe FPSMR Þelds are described in Table 31-6.Bits 0 1 2 3 4 5

MOTOROLA Chapter 31. FCC HDLC Controller 31-9Part IV. Communications Processor Module31.7 HDLC Receive Buffer Descriptor (RxBD)The HDLC controlle

31-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 31-4. FCC HDLC Receiving Using RxBDsBuffer00x002032-

MOTOROLA Chapter 31. FCC HDLC Controller 31-11Part IV. Communications Processor ModuleFigure 31-5 shows the FCC HDLC RxBD.Table 31-7 describes RxB

31-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe RxBD status bits are written by the HDLC controller aft

MOTOROLA Chapter 31. FCC HDLC Controller 31-13Part IV. Communications Processor ModuleTable 31-8 describes HDLC TxBD Þelds.The TxBD status bits ar

31-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe remaining TxBD parameters are as follows:¥ Data length

MOTOROLA Chapter 31. FCC HDLC Controller 31-15Part IV. Communications Processor ModuleFigure 31-8 shows interrupts that can be generated in the HD

31-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 31-8. HDLC Interrupt Event Example31.10 FCC Status

MOTOROLA Chapter 31. FCC HDLC Controller 31-17Part IV. Communications Processor ModuleTable 31-10 describes FCCS bits.Table 31-10. FCCS Register F

2-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview¥ Four independent execution units and two register ÞlesÑ BPU featuring static branch

31-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module

MOTOROLA Chapter 32. FCC Transparent Controller 32-1Chapter 32 FCC Transparent Controller 320320The FCC transparent controller functions as a high

32-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module32.1 FeaturesThe following is a list of the transparent con

MOTOROLA Chapter 32. FCC Transparent Controller 32-3Part IV. Communications Processor Module32.3.1 In-Line Synchronization PatternThe transparent

32-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module32.3.3 Transparent Synchronization ExampleFigure 32-2 shows

MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-1Chapter 33 Serial Peripheral Interface (SPI)330330The serial peripheral interface (SPI)

33-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module33.1 FeaturesThe following is a list of the SPIÕs main feat

MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-3Part IV. Communications Processor Module¥ When the SPI is a slave, SPICLK is the clock

33-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTo start exchanging data, the core writes the data to be sen

MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-5Part IV. Communications Processor Moduledrivers of SPI signals. The core must clear SPM

MOTOROLA Chapter 2. PowerPC Processor Core 2-5Part I. Overview¥ Integrated power managementÑ Three power-saving modes: doze, nap, and sleepÑ Automa

33-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe maximum sustained data rate that the SPI supports is SYS

MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-7Part IV. Communications Processor ModuleFigure 33-5. SPI Transfer Format with SPMODE[CP

33-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module33.4.1.1 SPI Examples with Different SPMODE[LEN] ValuesThe

MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-9Part IV. Communications Processor Modulethe data string selected is:msb r_stuv__ghij_kl

33-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 33-4 describes the SPCOM Þelds.33.5 SPI Parameter RA

MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-11Part IV. Communications Processor Module0x06 MRBLR Hword Maximum receive buffer length

33-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module33.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR

MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-13Part IV. Communications Processor Module33.7 The SPI Buffer Descriptor (BD) TableAs s

33-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Modulethan 8 bits, the data length should be even. For example, t

MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-15Part IV. Communications Processor Module33.7.1.2 SPI Transmit BD (TxBD)Data to be sen

2-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overvieware dispatched to their respective execution units from the dispatch unit at a maximum

33-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module33.8 SPI Master Programming ExampleThe following sequence

MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-17Part IV. Communications Processor Module8. Initialize the TxBD. Assume the Tx buffer i

33-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Moduleremains open. If the master sends 5 or more bytes, the TxBD

MOTOROLA Chapter 34. I2C Controller 34-1Chapter 34 I2C Controller340340The inter-integrated circuit (I2C¨) controller lets the MPC8260 exchange da

34-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleThe I2C receiver and transmitter are double-buffered, which

MOTOROLA Chapter 34. I2C Controller 34-3Part IV. Communications Processor ModuleWhen the I2C controller is master, the SCL clock output, taken dir

34-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module34.3.1 I2C Master Write (Slave Read)If the MPC8260 is the m

MOTOROLA Chapter 34. I2C Controller 34-5Part IV. Communications Processor ModuleIf the MPC8260 is the slave target of the read, prepare the I2C tr

34-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleAn MPC8260 I2C controller attempting a master read request c

MOTOROLA Chapter 34. I2C Controller 34-7Part IV. Communications Processor Module34.4.2 I2C Address Register (I2ADD)The I2C address register, show

MOTOROLA Chapter 2. PowerPC Processor Core 2-7Part I. Overview2.2.4.2 Load/Store Unit (LSU)The LSU executes all load and store instructions and pr

34-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 34-3 describes I2BRG Þelds. 34.4.4 I2C Event/Mask Reg

MOTOROLA Chapter 34. I2C Controller 34-9Part IV. Communications Processor ModuleTable 34-5 describes I2COM Þelds.34.5 I2C Parameter RAMThe I2C co

34-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module0x06 MRBLR Hword Maximum receive buffer length. DeÞnes the

MOTOROLA Chapter 34. I2C Controller 34-11Part IV. Communications Processor ModuleFigure 34-11 shows the RFCR/TFCR bit Þelds.Table 34-7 describes t

34-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module34.7 The I2C Buffer Descriptor (BD) TableAs shown in Figur

MOTOROLA Chapter 34. I2C Controller 34-13Part IV. Communications Processor Module34.7.1.1 I2C Receive Buffer Descriptor (RxBD)Using RxBDs, the CP

34-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module34.7.1.2 I2C Transmit Buffer Descriptor (TxBD)Transmit dat

MOTOROLA Chapter 35. Parallel I/O Ports 35-1Chapter 35 Parallel I/O Ports350350The CPM supports four general-purpose I/O portsÑports A, B, C, and

35-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module35.2 Port Registers Each port has four memory-mapped, read/

MOTOROLA Chapter 35. Parallel I/O Ports 35-3Part IV. Communications Processor Moduleto PDATx is still stored in the output latch, but is prevented

2-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview2.2.6 Memory Subsystem SupportThe processor core supports cache and memory management

35-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module35.2.4 Port Pin Assignment Register (PPAR)The port pin assi

MOTOROLA Chapter 35. Parallel I/O Ports 35-5Part IV. Communications Processor ModulePSOR bits are effective only if the corresponding PPARx[DDx] =

35-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module35.3 Port Block DiagramFigure 35-6 shows the functional blo

MOTOROLA Chapter 35. Parallel I/O Ports 35-7Part IV. Communications Processor Module35.4.1 General Purpose I/O PinsEach one of the port pins is i

35-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleFigure 35-7. Primary and Secondary Option ProgrammingIn the

MOTOROLA Chapter 35. Parallel I/O Ports 35-9Part IV. Communications Processor ModulePA25 FCC1: TxD[0] UTOPIA 8FCC1: TxD[8] UTOPIA 16MSNUM[0]1PA2

35-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModulePA18 FCC1: TxD[7] UTOPIA 8FCC1: TxD[15] UTOPIA 16FCC1: Tx

MOTOROLA Chapter 35. Parallel I/O Ports 35-11Part IV. Communications Processor ModulePA12 FCC1: RxD[2] UTOPIA 8FCC1: RxD[10] UTOPIA 16GND MSNUM[

35-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 35-6 shows the port B pin assignments.Table 35-6. Por

MOTOROLA Chapter 35. Parallel I/O Ports 35-13Part IV. Communications Processor ModulePB20 FCC2: RxD[6] UTOPIA 8FCC2: RxD[1] MII/HDLC/transp. nib

MOTOROLA Chapter 2. PowerPC Processor Core 2-9Part I. Overviewenvironment architecture (OEA), as well as the MPC8260 core implementation-speciÞcreg

35-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModuleTable 35-7 shows the port C pin assignments.PB7 FCC3: TXD[0

35-15 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModulePC26 Timer3: TOUT CLK6 GND TMCLK real-time counterBRGO1

35-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModulePC10 FCC1: TxD[2]UTOPIA 16 SCC3: CD SCC3: RENA EthernetGND

MOTOROLA Chapter 35. Parallel I/O Ports 35-17Part IV. Communications Processor ModuleTable 35-8 shows the port D pin assignments.Table 35-8. Port

35-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor ModulePD20 SCC4: RTS SCC4: TENAEthernetFCC1: RxD[2] UTOPIA 16GND

MOTOROLA Chapter 35. Parallel I/O Ports 35-19Part IV. Communications Processor Module35.6 Interrupts from Port CThe port C lines associated with

35-20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart IV. Communications Processor Module4. Write the corresponding SIMR (mask register) bit with a

MOTOROLA Appendix A. Register Quick Reference Guide A-1Appendix ARegister Quick Reference GuideA0A0This section provides a brief guide to the core r

A-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAAppendixesA.2 PowerPC RegistersÑSupervisor RegistersAll supervisor-level registers implemented on the

MOTOROLA Appendix A. Register Quick Reference Guide A-3AppendixesA.3 MPC8260-SpeciÞc SPRsTable A-2 and Table A-5 list SPRs speciÞc to the MPC8260.

2-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAPart I. Overview Figure 2-2. MPC8260 Programming ModelÑRegistersDSISRSPR 18DSISRData Address Register

A-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAAppendixes

MOTOROLA Index Index-1INDEXNumerics603e features list, 2-360x bus60x-compatible mode60x-compatible bus mode, 8-3address latch enable (ALE), 10-11BUFC

Index-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXVBR traffic, 29-12ATM TRANSMIT command, 29-90ATM-to-ATM data forwarding, 29-37ATM-to-TDM inte

MOTOROLA Index Index-3INDEXsystem interface unit (SIU)periodic interrupt timer, 4-5SIU block diagram, 4-1software watchdog timer, 4-7system configura

Index-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXCommunications processor (CP)block diagram, 13-5execution from RAM, 13-7features list, 13-4in

MOTOROLA Index Index-5INDEXcommand register example, 13-15CPCR, 13-11opcodes, 13-13overview, 13-11communications processor (CP)block diagram, 13-5exe

Index-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXmaster write (slave read), 34-4multi-master considerations, 34-5parameter RAM, 34-9programmin

MOTOROLA Index Index-7INDEXoverview, 18-1PDTEA, 18-4PDTEM, 18-4programming model, 18-3registers, 18-3SDMR, 18-4SDSR, 18-3serial configuration, 13-3se

Index-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXCxTx (chip-select signals), 10-74DDCM (IDMA channel mode), 18-18Digital phase-locked loop (DP

MOTOROLA Index Index-9INDEXFPSMRx, 28-7FTODRx, 28-7GFMRx, 28-3initialization, 28-14interrupt handling, 28-15interrupts, 28-13overview, 28-2parameter

MOTOROLA Chapter 2. PowerPC Processor Core 2-11Part I. OverviewAlthough the MPC8260 does not support ßoating-point arithmetic instructions, the FPR

Index-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXHHDLC modeaccessing the bus, 21-19bus controller, 21-17collision detection, 21-17, 21-20comm

MOTOROLA Index Index-11INDEXIDSR (IDMA event (status) register), 18-22IEEE 1149.1 test access portblock diagram, 12-2boundary scan register, 12-3inst

Index-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXprogramming model, 10-13PSDVAL, 10-12, 10-57register descriptions, 10-13SDRAM machine (synch

MOTOROLA Index Index-13INDEXserial peripheral interace (SPI)master mode, 33-3slow go, 17-2transparent modeoverview, 32-1serial communications control

Index-14 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXPPC_ALRH (60x bus arbitration high-level register), 4-28PPC_ALRL (60x bus arbitration low-le

MOTOROLA Index Index-15INDEXSCCE, 21-12SCCM, 21-12SCCS, 21-14I2C controllerI2ADD, 34-7I2BRG, 34-7I2CER, 34-8I2CMR, 34-8I2COM, 34-8I2MOD, 34-6IDMA emu

Index-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXTxBD, 26-33serial peripheral interface (SPI)SPCOM, 33-9SPIE, 33-9SPIM, 33-9SPMODE, 33-6syste

MOTOROLA Index Index-17INDEXtransparent mode, 23-12UART mode, 20-19SCCE registerEthernet mode, 24-21SCCM (SCC mask) registerBISYNC mode, 22-15HDLC mo

Index-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLAINDEXframe reception, 23-2frame transmission, 23-2inherent synchronization, 23-6in-line synchroni

MOTOROLA Index Index-19INDEXSerial peripheral interface (SPI)block diagram, 33-1clocking and pin functions, 33-2commands, 33-12configuring the SPI, 3