Motorola MVME2700 Series Manuel de service télécharger pdf (Page 93)

Programming Considerations

http://www.motorola.com/computer/literature 2-9

Interrupt Handling

The Raven ASIC, which controls PHB (PCI Host Bridge) MPU/local bus

interface functions on the MVME2700, performs interrupt handling as

well. Sources of interrupts may be any of the following:

❏ The Raven ASIC itself (timer or transfer error interrupts)

❏ The processor (processor self-interrupts)

❏ The Falcon chip set (memory error interrupts)

❏ The PCI bus (interrupts from PCI devices)

❏ The ISA bus (interrupts from ISA devices)

The following figure illustrates interrupt architecture on the MVME2700.

For details on interrupt handling, refer to the MVME2600/2700 Series

Single Board Computer Programmer’s Reference Guide.

Figure 2-3. MVME2700 Interrupt Architecture

11559.00 9609

PIB

(8529 Pair)

Processor

INT_

MCP_

RavenMPIC

INT

SERR_& PERR_

PCI Interrupts

ISA Interrupts

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Motorola MVME2700 Series Manuel de service Page 93