Motorola MC68VZ328 Manuel d'utilisateur

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. ©

2 MC68VZ328 Chip Errata MOTOROLA5 Real Time Int Status bits cannot be masked by interrupt enable bits.Effect:Unlike other interrupt status registers,

MOTOROLA MC68VZ328 Chip Errata 39 SPI1 transmits wrong bit if write to SPI1 TXFIFO during data exchanges.Effect:User cannot write to TXFIFO while SPI1

4 MC68VZ328 Chip Errata MOTOROLA12 Any change to PC or QC values in PLLFSR for certain VCO frequencies may cause PLL stability issues or jitter.Effect

MOTOROLA MC68VZ328 Chip Errata 5NOTES Freescale Semiconductor, I Freescale Semiconductor, Inc.For M

MC68VZ328CE/DInformation in this document is provided solely to enable system and software implementers to use Motorola products. There are no express