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CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Transition Module Preparation and Installation 10/100/1000BaseTx Connectors
100
5.5.5 10/100/1000BaseTx Connectors
Two 10/100/1000BaseTx RJ-45 connectors are located on the rear panel of the standard
version of the CPCI-6115-MCPTM to support Ethernet I/O from the CPCI-6115 SBC. The pin
assignments for these connectors are as follows:
5.5.6 COM1 And COM2 Connectors (MXP Version)
Four RJ-45 connectors are located on the panel of the MXP version of the CPCI-6115-MCPTM
to provide the interface to the COM1 and COM2 serial ports originating from the CPCI-6115
SBC. The CPCI-6115 only supports two serial ports, COM1 and COM2.
The COM1DIR jumper is a two position (three pin) jumper which controls the origin of the serial
port. In one position, COM1 from the CPCI-6115 is enabled (and thereby disabling it on the
CPCI-6115 front panel connector). In the other position, the connector is redirected to the PMC
I/O module 1. The COM2DIR jumper is a two position (three pin) jumper which controls the
origin of the serial port. In one position, COM2 from the CPCI-6115 is enabled. In the other
position, the connector is redirected to the PMC I/O module 2.
The pin assignments for this connector is as follows:
I2C_CLK - I2C Serial Clock for transition module EEPROM
I2C_DATA - I2C Serial Data for transition module EEPROM
Signal Descriptions
Table 5-9 10BaseT/100BaseTx Connector Pin Assignments
Pin Signal
1MDIO0+
2MDIO0-
3MDIO1+
4MDIO2+
5MDIO2-
6MDIO1-
7MDIO3+
8MDIO3-
Table 5-10 COM1, COM2 Connector Pin Assignments
Pin Signal
1DCD
2RTS
3GND
4TXD
- CPCI-6115 CompactPCI 1
- Single Board Computer 1
- Trademarks 2
- Contents 3
- List of Tables 10
- List of Figures 11
- About this Manual 13
- Abbreviations 14
- Conventions 16
- Summary of Changes 17
- Comments and Suggestions 18
- Safety Notes 19
- Operation 20
- Installation 20
- Cabling and Connectors 21
- Environment 22
- Sicherheitshinweise 23
- Schaltereinstellungen/Jumper 24
- Kabel und Stecker 26
- Umweltschutz 26
- Batterie 26
- Introduction 27
- 1.2 Standard Compliances 28
- 1.3 Ordering Information 29
- 2.1 Overview 31
- Requirements 32
- 2.3.2 Power Requirements 34
- 2.3.3 Thermal Requirements 34
- 2.4 Getting Started 37
- 2.5 Baseboard Preparation 38
- 2.5.3 J6, Bus Mode Selection 40
- 2.5.7 J20, Safe Start Header 42
- 2.6 Operating Modes 44
- 2.7 Installing Hardware 44
- Procedure 45
- Personal Injury or Death 46
- 2.9 Applying Power 49
- 3.1 Overview 51
- 3.2 Board Layout 52
- 3.4 ABORT/Reset Switch 54
- 3.5.7 CompactPCI Connector 58
- PCI_RSVD = PCI Reserved pin 62
- 3.5.14 Safe Start Header 67
- 3.5.15 Bus Mode Select Header 67
- 3.5.18 +/-12 V Present Header 68
- Functional Description 69
- 4.2 Block Diagram 70
- 4.3 General Description 71
- 4.3.2 Processor 72
- 4.3.3 L3 Cache 72
- 4.3.4.12 Interrupt Controller 76
- 4.3.4.13 PCI Bus Arbitration 76
- 4.3.4.14 Board Reset Logic 77
- 4.3.5 System Memory 81
- 4.3.6 Flash Memory 82
- 4.3.8 TL16C550C UART Devices 83
- 4.3.9 System Registers 83
- 4.3.10 Serial EEPROM Devices 83
- 4.3.11 PCI Bus 0.0 83
- 4.3.12 PCI Bus 1.0 83
- 4.3.13 IDE Controller 84
- 4.3.15 CompactPCI Bus 84
- 4.3.16 PMC Slots 84
- 4.4 Miscellaneous 86
- 4.4.3 Onboard Power Supplies 89
- 4.4.4 Hot Swap Support 89
- 4.4.5 Hot Swap Process 89
- 5.2 Block Diagram 92
- 5.4 Rear Panel Connectors 94
- 5.5.2.1 Host IO Connectors 96
- 5.5.2.2 PMC I/O Connectors 98
- 5.6 Jumper Settings 104
- 5.7 Functional Description 105
- 5.7.3 Hot-Swap Support 106
- 5.7.4 Serial EEPROM 106
- 5.7.5 PMC I/O Modules 106
- 5.7.7 PMC I/O Module 110
- 5.7.9 PMC I/O Connector 112
- 5.7.10 Host I/O Connector 112
- 5.8 Installing the PIM 113
- Figure 5-9 Installing the PIM 114
- Remote Start via the PCI Bus 117
- MOTLoad Firmware 119
- 7.4 MOTLoad Commands 120
- 7.6 MOTLoad Tests 120
- 7.7 Using MOTLoad 121
- 7.7.2 Command Line Help 122
- 7.7.3 Command Line Rules 122
- 7.8 MOTLoad Command List 123
- Memory Maps 127
- 8.2.2 Processor Memory Map 128
- 8.2.3 Default PCI Memory Map 129
- 8.2.5 System I/O Memory Map 131
- 8.2.7 CompactPCI Memory Map 131
- 8.2.9 L1, L2 and L3 Cache 132
- 8.2.10 System Memory 132
- A Related Documentation 133
- A.3 Related Specifications 134
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