Motorola CPCI-6115 Manuel de service télécharger pdf (Page 73)

MV64360 System Controller Functional Description

CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

z One I

C interface

z One four-channel Independent DMA controller

All of the above interfaces are connected through a cross-bar fabric. The cross-bar enables

concurrent transactions between units. For example, the cross-bar can simultaneously control

the:

z Gigabit Ethernet MAC fetching a descriptor from the integrated SRAM

z CPU reading from the DRAM

z DMA moving data from the device bus to the PCI bus

4.3.4.1 MV64360 CPU Bus Interface

The CPU interface (master and slave) operates at 133 MHz using either the 60x or MPX bus

modes. The bus mode is jumper selectable. The CPU bus has 36-bit address and 64-bit data

busses. The MV64360 fully supports PowerPC cache coherency. The MV64360 supports up to

eight pipelined transactions per processor. There are 21 address windows supported in the

CPU interface:

z Four for DDR SDRAM chip selects

z Five for device chip selects

z Five for PCI_0 interface (4 memory + one I/O)

z Five for PCI_1 interface (4 memory + one I/O)

z One for the MV64360 integrated SRAM

z One for the MV64360 internal registers SRAM

Each window is defined by Base and Size registers and can decode up to 4 GB space (except

for the integrated SRAM which is fixed at 256 KB). Refer to the MV64360 Data Sheet for

additional information and programming details.

4.3.4.2 MV64360 DDR SDRAM Interface

The CPCI-6115 supports three banks of DDR SDRAM using 256 megabit, 512 megabit or 1

gigabit DDR SDRAM devices onboard. A 133 MHz (DDR266) operation is used when two or

three banks are populated. The SDRAM supports ECC. The SDRAM controller contains four

transaction queues - two write buffers and two read buffers. The SDRAM controller does not

necessarily issue SDRAM transactions in the same order that it receives the transactions. The

MV64360 supports full PowerPC cache coherency between CPU L1/L2 and L3 caches and

SDRAM. Each access to the SDRAM may result in snoop transaction initiated by the MV64360

on the CPU bus. The SDRAM controller supports a wide range of SDRAM timing parameters

to meet the needs of current and future DDR SDRAM devices. These parameters can be

configured through the SDRAM Mode register and the SDRAM Timing Parameters register.

Refer to the MV64360 Data Sheet for additional information and programming details.

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Motorola CPCI-6115 Manuel de service Page 73