Motorola MPC5200 Manuel d'utilisateur télécharger pdf (Page 20)

Bright Star Engineering, Inc. Page 15

Table 14. Connector pin description

Signal Name Description

ENET_RX_P/N Ethernet receive differential pair (100 )

ENET_TX_P/N Ethernet transmit differential pair (100 )

ETH13_J1850_RX

J1850 Receive signal (Requires Ethernet to be in 7-wire mode, programmable)

ETH16_INT

Programmable GPIO_INT (Requires Ethernet to be in 7-wire mode)

ETH17_GPIO_WKUP Programmable GPIO_WKUP (Requires Ethernet to be in 7-wire mode)

ETH4_J1850_TX

3,4

J1850 Receive signal (Requires Ethernet to be in 7-wire mode, programmable)

GND Ground, reference/power return plane

GPIO_WKUP_6 Direct connection to MPC5200 GPIO_WKUP_6 pin, C15

GPIO_WKUP_7 Direct connection to MPC5200 GPIO_WKUP_7 pin, C12

HRST_L Hardware Reset, active low, I/O, 5.6 k pull-up

I2C2_CLK I

C channel 2 clock signal, 10 k pull-up

I2C2_SDA I

C channel 2 serial data/address signal, 10 k pull-up

IRQ0 Interrupt Request 0, 5.6 k pull-up

IRQ1 Interrupt Request 1, 5.6 k pull-up

IRQ3 Interrupt Request 3, 5.6 k pull-up

LNK_LED_L Ethernet Link LED, active low, 10 mA sink current recommended

LP_ACK LocalPlus Acknowledge signal, 5.6 k pull-up

LP_ALE_L

LocalPlus Address Latch Enable signal, active low

LP_CS2_L LocalPlus Chip Select 2, active low, 5.6 k pull-up

LP_CS3_L LocalPlus Chip Select 3, active low, 5.6 k pull-up

LP_CS4_L LocalPlus Chip Select 4, active low, 5.6 k pull-up

LP_CS5_L LocalPlus Chip Select 5, active low, 5.6 k pull-up

LP_OE_L LocalPlus Output Enable, active low

LP_R_W_L

LocalPlus Read (active high)/Write (active low) signal

LP_TS_L

LocalPlus Transfer Start, active low

MRST_L Master Reset input, 5.6 k pull-up

NC_J1_191 No Connection

EXT_AD[31:0] PCI multiplexed Address/Data bus, LocalPlus Address/Data bus. EXT_AD in

LocalPlus mode.

PCI_CBE_L[3:0] PCI Byte Enable signals, active low

PCI_CLK_OUT PCI clock output, 33.000 MHz

PCI_DEVSEL_L PCI Device Select, active low, 5.6 k pull-up

PCI_FRAME_L PCI Frame signal, active low, 5.6 k pull-up

PCI_GNT_L PCI Grant signal, active low

PCI_IDSEL PCI ID Select signal

PCI_IRDY_L PCI Initiator Ready signal, active low, 5.6 k pull-up

PCI_PAR PCI Parity signal

PCI_PERR_L PCI Parity Error signal, active low, 5.6 k pull-up

PCI_REQ_L PCI Request signal, active low

PCI_RESET_L PCI Reset input, active low, 5.6 k pull-up

PCI_SERR_L PCI System Error signal, active low, 5.6 k pull-up

PCI_STOP_L PCI Stop signal, active low, 5.6 k pull-up

PCI_TRDY_L PCI Target Ready signal, active low, 5.6 k pull-up

POR_RST_L Power-On Reset, output from reset controller, active low

PSC1_[4:0]

PSC port 1, bit 3 has a 10 k pull-up. Note 4 applies to bit 0 only

PSC2_[4:0] PSC port 2, bit 3 has a 10 k pull-up

PSC6_[3:0] PSC port 6, bit 1 10 k pull-up

SRST_L Soft reset, active low, I/O, 5.6 k pull-up

TCK

TDI

TDO

TMS

TRST_L

JTAG Test interface, external pull-ups are not required.

TEST_SEL_0 JTAG scan enable input, PLL bypass input, CK_STOP output

TIMER_0_CAN2_TX

TIMER_1_CAN2_RX

TIMER_2_SPI_MOSI

TIMER_3_SPI_MISO

TIMER_4_SPI_SS

TIMER_5_SPI_SCK

TIMER_6

Timer Port. Preferred port for CAN2 and SPI. In this mode, Timer 6 is a GPIO.

Timer port, bit 7 is not available at the connector, it is used internally as

FLASH_CE_L.

USB_1_UART4_RTS

USB_4_UART4_CTS

USB_5_UART5_RXD

USB_6_UART5_TXD

USB Port, must be configured as UART4/5. UART4 is reserved as the console port

and the RxD and TxD signals are true EIA/TIA 232 levels. RTS and CTS are

optional. CTS for both UARTs (bits 4 and 8) are pulled-up. Bits 0 and 9 are used

internally as SEL_E10_L and ENET_RST_L respectively.

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Motorola MPC5200 Manuel d'utilisateur Page 20

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