Motorola MVME2700 Series Manuel de service télécharger pdf (Page 96)

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Operating Instructions

Processor/Memory Domain

The MPC750 processor can operate in both big-endian and little-endian

mode. However, it always treats the external processor/memory bus as

big-endian by performing address rearrangement and reordering when

running in little-endian mode. The MPC registers in the Raven MPU/PCI

bus bridge controller ASIC and the Falcon memory controller chip set, as

well as DRAM, ROM/Flash, and system registers, always appear as

big-endian.

Role of the Raven ASIC

Because the PCI bus is little-endian, the Raven performs byte swapping in

both directions (from PCI to memory and from the processor to PCI) to

maintain address invariance while programmed to operate in big-endian

mode with the processor and the memory subsystem.

In little-endian mode, the Raven reverse-rearranges the address for PCI-

bound accesses and rearranges the address for memory-bound accesses

(from PCI). In this case, no byte swapping is done.

PCI Domain

The PCI bus is inherently little-endian. All devices connected directly to

the PCI bus operate in little-endian mode, regardless of the mode of

operation in the processor’s domain.

PCI and SCSI

SCSI is byte-stream-oriented; the byte having the lowest address in

memory is the first one to be transferred regardless of the endian mode.

Since the Raven ASIC maintains address invariance in both little-endian

and big-endian modes, no endian issues should arise for SCSI data.

Big-endian software must still take the byte-swapping effect into account

when accessing the registers of the PCI/SCSI device, however.

PCI and Ethernet

Ethernet is also byte-stream-oriented; the byte having the lowest address

in memory is the first one to be transferred regardless of the endian mode.

Since the Raven maintains address invariance in both little-endian and

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Motorola MVME2700 Series Manuel de service Page 96