Motorola DSP56303 Manuel d'utilisateur télécharger pdf (Page 2)

2 DSP56303 Product Brief

DSP56303 Features

DSP56303 FEATURES

• High-performance DSP56300 core

– 66/80/100 Million Instructions Per Second (MIPS) with a 66/80/100 MHz clock

– Object code compatible with the DSP56000 core

– Highly parallel instruction set

– Fully pipelined 24 x 24-bit parallel multiplier-accumulator

– 56-bit parallel barrel shifter

– 24-bit or 16-bit arithmetic support under software control

– Position independent code support

– Addressing modes optimized for DSP applications

– On-chip instruction cache controller

– On-chip memory-expandable hardware stack

– Nested hardware DO loops

– Fast auto-return interrupts

– On-chip concurrent six-channel DMA controller

– On-chip Phase Lock Loop (PLL) and clock generator

– On-Chip Emulation (OnCE™) module

– Joint Test Action Group (JTAG) Test Access Port (TAP)

– Address tracing mode that reflects internal accesses at the external port

• On-chip memories

– Program RAM, Instruction Cache, X data RAM, and Y data RAM size are programmable:

– 192 × 24-bit bootstrap ROM

Instruction

Cache

Switch

Mode

Program

RAM Size

Instruction

Cache Size

X Data RAM

Size

Y Data Ram

Size

disabled disabled 4096 × 24-bit 0 2048 × 24-bit 2048 × 24-bit

enabled disabled 3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit

disabled enabled 2048 × 24-bit 0 3072 × 24-bit 3072 × 24-bit

enabled enabled 1024 × 24-bit 1024 × 24-bit 3072 × 24-bit 3072 × 24-bit

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Motorola DSP56303 Manuel d'utilisateur Page 2