Motorola CPU32 Manuel d'utilisateur télécharger pdf (Page 93)

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101

Instruction Set Summary

3-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA

functions, software supports remainder and integer part; the FPU also supports the

nontranscendental operations of absolute value, negate, and test.

Most ﬂoating-point instruction descriptions include an operation table. This table lists the

resulting data types for the instruction based on the operand,s input. Table 3-20 is an

operation table example for the FADD instruction. The operation table lists the source

operand type along the top, and the destination operand type along the side. In-range

numbers are normalized, denormalized, unnormalized real numbers, or integers that are

converted to normalized or denormalized extended-precision numbers upon entering the

FPU.

NOTES:

1.If either operand is a NAN, refer to 1.6.5 NANs for more information.

2.Returns +0.0 in rounding modes RN, RZ, and RP; returns –0.0 in RM.

3.Sets the OPERR bit in the FPSR exception byte.

For example, Table 3-20 illustrates that if both the source and destination operand are

positive zero, the result is also a positive zero. If the source operand is a positive zero and

the destination operand is an in-range number, then the ADD algorithm is executed to obtain

the result. If a label such as ADD appears in the table, it indicates that the FPU performs the

indicated operation and returns the correct result. Since the result of such an operation is

undeﬁned, a NAN is returned as the result, and the OPERR bit is set in the FPSR EXC byte.

In addition to the data types covered in the operation tables for each ﬂoating-point

instruction, NANs can also be used as inputs to an arithmetic operation. The operation

tables do not contain a row and column for NANs because NANs are handled the same way

for all operations. If either operand, but not both operands, of an operation is a nonsignaling

NAN, then that NAN is returned as the result. If both operands are nonsignaling NANs, then

the destination operand nonsignaling NAN is returned as the result.

If either operand to an operation is a signaling NAN (SNAN), then the SNAN bit is set in the

FPSR EXC byte. If the SNAN exception enable bit is set in the FPCR ENABLE byte, then

the exception is taken and the destination is not modiﬁed. If the SNAN exception enable bit

is not set, setting the SNAN bit in the operand to a one converts the SNAN to a nonsignaling

NAN. The operation then continues as described in the preceding paragraph for

nonsignaling NANs.

Table 3-20. Operation Table Example (FADD Instruction)

DESTINATION

SOURCE

+ In Range – + Zero – + Inﬁnity –

In Range +

–

ADD ADD +inf –inf

Zero +

–

ADD

+ 0.0 0.0

0.0

–0.0

+inf –inf

Infinity +

–

+inf

–inf

+inf

–inf

+inf NAN

NAN

–inf

1 2 ... 88 89 90 91 92 93 94 95 96 97 98 ... 645 646

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Motorola CPU32 Manuel d'utilisateur Page 93

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