Motorola Pro FLX Manuel d'utilisateur télécharger pdf (Page 31)

Design and Implementation of a Practical FLEX Paging Decoder

Grayson Wireless 23

T-Avg

R3R4

T-Low

T-High

Max

Min

2.49 K

Ω

4.87 K

Ω

4.87 K

Ω

2.49 K

Ω

Low

Middle

High

LM339

Figure 3-6

Resistor divider used to detect threshold voltage levels

Figure 3-6 also shows how these levels are used at negative inputs into a comparator (LM339).

If the input voltage (V

) is less than the threshold then the output of the LM339 is a TTL low,

otherwise the output is TTL high. The limited data (High, Middle, and Low) is then

simultaneous clocked into three shift registers. The sampled data can then be directly read by the

microprocessor. Figure 3-7 shows a block diagram of how this occurs. The microprocessor can

control the sample rate. The approach taken with this design was to sample at 8 times the baud

rate. Thus the sample clock will be running at 12800 Hz for 1600 baud or 25600 Hz for 3200

baud.

Figure 3-7

Limited Data into Microprocessor

The microprocessor must perform symbol determination and symbol clock synchronization in

order to accurately recover the data.

Low

Middle

High

8-Bit Shift

Clock

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 73 74

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Motorola Pro FLX Manuel d'utilisateur Page 31