Motorola Pro FLX Manuel d'utilisateur télécharger pdf (Page 32)

Design and Implementation of a Practical FLEX Paging Decoder

Grayson Wireless 24

The symbol determination was performed by first determining the most significant bit (MSB).

Bit determination is the majority bit in the shift register or metric of data. This was implemented

with a look up table for speed. Because of timing jitter, which is corrected for by the

synchronization, and symbol transition time, not all 8 samples are used to determine the bit. For

the MSB, the middle 6 samples were used to determine the bit and only the middle 4 samples

were used to determine the least significant bit (LSB). The MSB is determined from the middle

sample shift register. Once the MSB is determined, the LSB is determined from the either the

low sample shift register or high sample shift register based on the MSB. If the MSB is a logic 1,

then LSB is determined from the high sample shift register. The Gray coding requires that result

of this LSB be inverted so that symbol associated with the highest deviation be 10. If the MSB is

a logic 0, then LSB is determined from the low sample shift register. The Gray coding

requirement is correct with this LSB since the symbol associated with the lowest deviation will

be 00.

Symbol determination is using the sampled data to determine one of the four possible symbols

for 4-FSK or one of two possible symbols for 2-FSK. The ideal symbol determination would be

to integrate over the entire symbol and the result would map into one of the possible symbols.

This approach is very similar but a few variations. First the data from the discriminator are

limited to a logic 1 or 0 thus there is no resolution of how close each sample is to the threshold

voltage. Also the data is only sampled 8 times in a symbol period. An ideal integrator would

have an infinite number of samples. Also all 8 samples might not be in the same symbol period

due to clock variations. Adjustment of the sample clock is performed with the symbol clock

synchronization algorithm.

The symbol timing is determined with each MSB. The 8 samples in the middle shift register are

examine to see where the bit energy is centered. If the bit energy is centered around the middle,

which is bits 3 or 4, then the next sample will be taken in 8 clocks. If the bit energy is centered

toward the more recent samples, which is bits 0, 1, or 2, the next sample will be taken in 9

clocks. This is a lag condition in which the sample clock is delayed so that the next bit will be

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Motorola Pro FLX Manuel d'utilisateur Page 32