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Design and Implementation of a Practical FLEX Paging Decoder

Grayson Wireless 25

centered. If the bit energy is centered toward the older samples which is bits 5, 6 or 7, the next

sample is taken in 7 clocks. This is lead condition in which the sample clock is increased so that

the next bit will be centered. Just as the bit determination is implemented with a look up table

for speed, so is the symbol timing.

The sample clock used in this design is divided down by a crystal that is rated at

100 ppm so

this means the sample clock can be off by

0.01 %. For the data to slip 1/8 of a symbol time it

would take 1/8 divided by 0.01% or 1250 bits minimum before a symbol timing needs to be

adjusted.

3.3 Microprocessor software implementation

The microprocessor used in this design was a Dallas 80C320 which is a fast 80C31/80C32-

compatiable microcontroller [Dal 93]. The DS80C320 uses the 8051 instruction set with an

average speed improvement of 2.5 time faster. The microprocessor software was implemented

using some of the inherent features of microprocessor. The microprocessor had two processes

running at the same time: interrupt processing and main processing. The interrupt processing

was used for the time critical process of symbol determination and collection and maintaining

symbol timing. The main processing was used to examine the collected data for the FLEX

protocol and report the formatted data.

The previous section described how the microprocessor determined the symbol and maintained

clock synchronization. This is what is occurring during the interrupt processing. Figure 3-8 is

the block diagram for the interrupt processing. The processes Determine Bit and Determine Next

Symbol Time in Figure 3-8 are implemented using a table look-up of the 8-bit sampled value.

This allows fast determination of bit and next timing value. The symbol timing is loaded into a

counter that decrements with each sample clock. When the count goes to zero, the interrupt

occurs. The main processing loop is temporarily suspended while the interrupt is processed.

Figure 3-8 is only provided to illustrate how the software process is implemented. For a

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Motorola Pro FLX Manuel d'utilisateur Page 33