Motorola Pro FLX Manuel d'utilisateur télécharger pdf (Page 36)

Design and Implementation of a Practical FLEX Paging Decoder

Grayson Wireless 28

returns a 2-bit error correction factor. The software then sends the 21 data bits (see Section 2.3.3

for codeword structure) and the 2-bit error correction factor via the serial port. The 2-bit error

correction factor is similar to the one described in the reporting of the Sync1 detected.

All data that is now collected is with new baud rate of 1600 or 3200 and the bits/symbol is either

1 (2-FSK) or 2 (4-FSK). Sync2 is collected first and compared to the expected Sync2. If Sync2

is not within 3 bits of expected then the software reports an error with Sync2, otherwise a good

Sync2 is reported with a 2-bit error factor (not shown in block diagram). The 11 blocks of

interleave are now collected. The block number is shown as “n” in the block diagram. The 160

ms of data are collected. The data is de-interleaved by simply reversing the interleave process

described in section 2.3.2. The number of codewords that will be de-interleaved is 8, 16, or 32

based on the respective data rate 1600, 3200, or 6400 bps. For each codeword, the BCH forward

error correction algorithm is employed on the codeword. The software then sends the 21 data

bits, the block number, word number interleaved, and the 2-bit error correction factor via the

serial port.

The standard BCH decode algorithm as defined in [Lin 83] involves three steps. Compute the

syndrome, S, from the received data, determine the error-location polynomial,

(z), from the

syndromes, and then determine the error-location numbers by finding the roots of the error-

location polynomial. There are two syndromes that need to be calculated with the (31,21) BCH:

S1 and S3. Both are calculated by dividing the received pattern by the minimum polynomials

M1 and M3.

M1 = X

M3 = X

The routine used to calculate this division is quite simple in an 8-bit micro-processor. It requires

two working division registers: m1 and m3. Each received bit is shifted into the LSB of the

working m1 register. If the bit in the 5

bit location of m1 is a logic one then m1 is exclusive

ORed (XORed) with the value 0x25, otherwise m1 is not changed. The same process is

performed with the working m3 but the value XORed is 0x3D. This accomplishes in software

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Motorola Pro FLX Manuel d'utilisateur Page 36