Motorola MSC8101 ADS Manuel d'utilisateur télécharger pdf (Page 13)

8 PFC_DDD_v1.3.doc

5 Hardware Description

This section describes the Packet Telephony Farm Card Hardware. The Hardware architecture has

been partitioned into the following logical sections: Aggregator, DSP Processing Array, General Board

Configuration, Firmware and PFC Base Card.

5.1 Board Architecture

The board architecture of the Packet Telephony Farm Card is shown in Figure 3.

Figure 3. Packet Telephony Farm Card Architecture

This can be split into 2 main blocks

1. MSC8101 Aggregator Processor

2. MSC8102 Farm

Under typical operating conditions the MSC8101 is used to terminate ATM or 10/100BaseT Ethernet

packet traffic from a host card via its PTMC interface, with the subsequent data placed in the

MSC8101’s internal SRAM or external SDRAM. The data is then distributed to the MSC8102 farm for

processing via the MSC8102 DSI port with the FPGA performing the 60x bus to DSI translation

(NOTE: the FPGA has been incorporated to allow synchronous DSI transfer – it is not required for

asynchronous DSI transfers). After MSC8102 processing the data is dispatched through the MSC8102

TDM interfaces to the PTMC CT Bus.

5.2 MSC8101 Aggregator & 60x Bus Interface

The Aggregator terminates the packet protocol and transfers Media Data to and from the DSP Array

through its 60x bus. The 60x interface to the MSC8102 DSI can be configured as 32 or 64-bit wide.

When configured for 32-bit operation an external host can access the host port (HDI16) of the

MSC8101 aggregator for bootstrap and ongoing data exchange and control. 4 MB of 8-bit wide Flash

is connected to the MSC8101 60x bus for configuration, boot and execution code (for all 6 DSPs). 8

MBytes of 32-bit wide SDRAM also hangs off this bus to provide adequate storage during real time

operation. It should be noted that the address bus is latched to the SDRAM and Flash memories due to

the 60x compatible mode used (when running in DSI Synchronous mode). The data bus is un-buffered

to the memories and FPGA but buffered for the HDI16 port. The SDRAM is not required for normal

Aggregation functions and has been incorporated purely for maximum flexibility.

Table 9 details the MSC8101 Chip selects used for the 60x bus devices.

PN2

MSC8101

FPGA

16MB

SDRAM

8MB

SDRAM

4MB

FLASH

LATCH

MUX

64/32-bit

60x

32/64-bit

DSI

Ethernet

(MII 1)

UTOPIA

Ethernet

(RMII)

Host

Buffer

FCC1

FCC2

SMC2

MUX

FPGA

Ethernet

(MII 2)

LATCH

8-bit32-bit

CT Bus

32-bit

PN2

PN4

PN5

PN3

CPORT GMII

Interface

PN1

16MB

SDRAM

CT Bus

32-bit

16MB

SDRAM

CT Bus

32-bit

16MB

SDRAM

CT Bus

32-bit

16MB

SDRAM

CT Bus

32-bit

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

PN2

MSC8101

FPGA

16MB

SDRAM

8MB

SDRAM

4MB

FLASH

LATCH

MUX

64/32-bit

60x

32/64-bit

DSI

Ethernet

(MII 1)

UTOPIA

Ethernet

(RMII)

Host

Buffer

FCC1

FCC2

SMC2

MUX

FPGA

Ethernet

(MII 2)

LATCH

8-bit32-bit

CT Bus

32-bit

PN2

PN4

PN5

PN3

CPORT GMII

Interface

PN1

16MB

SDRAM

CT Bus

32-bit

16MB

SDRAM

CT Bus

32-bit

16MB

SDRAM

CT Bus

32-bit

16MB

SDRAM

CT Bus

32-bit

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

MSC8102

DSI

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Motorola MSC8101 ADS Manuel d'utilisateur Page 13

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