Motorola M68CPU32BUG Manuel d'utilisateur télécharger pdf (Page 11)

MC68332TUT/D MOTOROLA

2.5.2.4 XFC and V

DDSYN

Noise on the XFC, V

DDSYN

, and V

SSI

pins causes frequency shifts in CLKOUT. The XFC filter capacitor and

the V

DDSYN

bypass capacitors should be kept as close to the XFC and V

DDSYN

pins as possible, with no

digital logic coupling to either XFC or V

DDSYN

. The ground for the V

DDSYN

bypass capacitors should be tied

directly to the V

SSI

ground plane. If possible, route V

DDSYN

and V

SSI

as separate supply runs or planes.

DDSYN

may require an inductive or resistive filter to control supply noise.

A V

DDSYN

resistive filter would consist of a 100 to 500 Ω resistor from V

to V

DDSYN

and a 0.1-µF bypass

capacitor from V

DDSYN

to V

SSI

. The proper values for the resistor and capacitor can be determined by ex-

amining the frequency of the V

DDSYN

noise. The RC time constant needs to be large enough to filter the

supply noise. An inductive filter would replace the resistor with an inductor.

The low-pass filter requires an external low-leakage capacitor, typically 0.1 µF with an insulation resistance

specification as high as practical. The main criterion is that the capacitor be low-leakage because leakage

affects frequency stability and accuracy. Do not use a tantalum capacitor. Although the

SIM User’s Manual

recommends an insulation resistance of 30,000 MΩ, this value may not be necessary in all applications. For

most consumer (room temperature) applications, polystyrene capacitors are recommended. See Figure 7

for a recommended circuit.

NOTE

Some published errata sheets and Revision1 of the

MC68332 User’s Manual

rec-

ommend a filter circuit that includes an 18 kΩ resistor for a high stability operating

environment.Subsequent investigation has shown that, when this circuit is used, if

there is leakage (about 50 kΩ) between the XFC pin and the power supply, the

MCU may not come out of reset because the internal VCO lock detect circuitry

does not operate properly. Use the circuit shown in Figure 7 instead.

Figure 7 Conditioning the XFC and V

DDSYN

Pins

2.5.2.5 Evaluating Oscillator Performance

Once an entire oscillator circuit is built, it is very important to evaluate circuit characteristics. Of particular

interest is how the oscillator starts. If the oscillator starts in a metastable state that persists for several hun-

dred milliseconds, it is quite possible that this state will persist until the MCU releases reset and tries to start

fetching instructions. When this happens, the PLL may well be operating at a frequency far greater than the

maximum specified for the MCU. Any variation in the input frequency of the PLL is multiplied by the feed-

back ratio of the PLL. If the MCU starts operating, i.e., reset is released and the internal clocks are gated to

the internal buses, while the oscillator is operating at an overtone or first harmonic, the MCU will probably

enter an inoperative state in which it cannot be restarted by a hardware reset. In this case, the only option

is to turn the system power off and then attempt a power-on reset.

Because oscillators are very sensitive circuits, malfunctions are difficult to diagnose by conventional means

such as probing the input and output with an oscilloscope. The capacitance of a scope probe can be large

compared to the effective capacitance of the particular node of the oscillator that is probed. This added ca-

pacitance can cause an errant oscillator to move to a more stable region where it appears to work correctly

332TUT XFC CONN

* MAINTAIN LOW LEAKAGE ON THE XFC NODE.

DDSYN

0.01µF

0.1µF

XFC

SSI

0.1µF

C3 C1

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 55 56

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Motorola M68CPU32BUG Manuel d'utilisateur Page 11

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