Motorola DSP56305 Manuel d'utilisateur Page 62
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- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
MOTOROLA Optimizing DSP56300/DSP56600 Applications 5-1
This section
discusses the
instruction cache
and some other
memory features.
Section 5
INSTRUCTION CACHE AND MEMORY FEATURES
The DSP56300 supports running programs from the external
memory, but each fetch of a program word inserts wait states
(depending on the memory type, with a minimum of one wait state
per fetch). The performance of such a program may be severely
impaired, but the user is able to reduce his system cost by using
slower and cheaper memory devices, such as slow EPROMs and
Dynamic RAMs. The common way to maintain program speed with
these wait states is program overlays, which are handled by
software. The instruction cache allows an external code to execute
automatically at the highest speed of on-chip execution without the
need for program overlays, yet use slow memory devices. Detailed
information about the instruction cache can be found in Section 5
of the
DSP56300 Family Manual
.
5.1 THE INSTRUCTION CACHE
The instruction cache includes a controller (part of the DSP56300
core) and a cacheable memory array (part of the on-chip Program
RAM) that may be used to store the cached instructions. When the
cache controller is disabled (the Cache Enable bit in the SR is
cleared), the cacheable memory behaves like regular Program RAM,
and is accessible to the user as part of the internal program memory
space. When the cache controller is enabled (the Cache Enable bit in
the SR is set), the cacheable memory is used by the cache controller
to store the cached instructions, and is not accessible to the user. The
address space onto which it was previously mapped is now
considered external. When the cache is enabled, the cache controller
checks each external program address before it is fetched. If it was
not fetched before, it is a cache “miss”. The address is fetched from
the external memory, and stored in the cache memory in parallel to
it's execution. If that address was fetched before, it is a cache “hit”,
meaning that a copy of the instruction was previously stored in the
cache. The cache controller blocks the external access and the
instruction is fetched from the cache. From the pipeline's point of
view, an external fetch with a cache “hit” is equivalent to an internal
fetch—no wait states are inserted.
- DSP56300/DSP56600 1
- Digital Signal 1
- Processors 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 6
- LIST OF TABLES 7
- INTRODUCTION 8
- 1.2 DSP56600 CORE FAMILY 9
- Table 1-1 11
- Introduction 12
- Description and Use 13
- Application Note Structure 14
- 1.4.3 Appendixes 15
- DATA OPERATIONS 16
- DSP56300 Family Manual 21
- 2.3 THE MAX INSTRUCTION 22
- 2.4 USING THE BARREL SHIFTER 23
- Data Operations 24
- Using the barrel shifter 24
- DSP56300 26
- DSP56600 Family 26
- Double precision arithmetic 27
- INSTRUCTIONS 28
- PROGRAM CONTROL 30
- Program Control 31
- Hardware Loops 31
- 3.2 THE HARDWARE STACK 32
- DSP56600 Family Manuals 35
- 3.3 USING THE STACK EXTENSION 36
- Using the Stack Extension 37
- EXTENSION 39
- Conditional DALU Instructions 40
- 3.6 PC RELATIVE INSTRUCTIONS 42
- DSP56600 Family Manual 43
- 3.7 USING FAST INTERRUPTS 46
- Using Fast Interrupts 48
- USING THE DMA 50
- Using the DMA 51
- Using Slow, Low-Cost Memories 54
- 4.4 SERVICING A PERIPHERAL 55
- Servicing a Peripheral 56
- Section 5 62
- 5.1 THE INSTRUCTION CACHE 62
- 5.1.1 Cache Sectors 64
- The Instruction Cache 65
- 5.1.3 Cache Burst Mode 67
- 5.2 MEMORY SWITCH 70
- Memory Switch 71
- 5.3 USING THE BOOTSTRAP ROM 72
- Using the Bootstrap ROM 73
- PIPELINE INTERLOCKS 74
- Pipeline Interlocks 75
- Data ALU Pipeline Interlocks 75
- DSP56000 Family Manual 76
- INTERLOCKS 80
- Interlocks 80
- 6.3 STACK EXTENSION DELAYS 81
- Interlocks? 83
- COMPACT OPCODE USE 86
- Instructions 87
- Compact Opcode Use 89
- Cycle Count of an Instruction 89
- 7.2 ADDRESSING MODES 90
- 7.2.2 Short Addressing Mode 91
- 7.2.3 Short Immediate Mode 91
- 7.2.5 Register Addressing 92
- 7.2.6 Word Count 92
- 7.3 PERIPHERAL ADDRESSING 92
- 7.4 SPECIAL INSTRUCTIONS 93
- 7.4.1 Dual Data Spaces 93
- 7.4.3 Clearing Registers 94
- Special Instructions 95
- SAVING POWER 96
- A.1.2 Stop Standby Mode 97
- A.1.3 Low-Power Clock Divider 97
- Saving Power 98
- Disabling Functional Blocks 98
- DEBUG AND TEST SUPPORT 100
- B.2 JTAG PORT FEATURES 101
- B.3 ADDRESS TRACING 102
- Debug and Test Support 103
- Address Tracing 103
- USING THE PROFILER 104
- C.3 THE PROFILING REPORT 105
- C.3.1 Basic Report 105
- C.3.2 Symbol Report 106
- Using the Profiler 107
- C.3.4 Code Coverage Report 108
- C.3.5 Basic Subroutine Report 109
- C.3.8 Subroutine Call Report 111
- C.4 USING THE PROFILE REPORT 111
- How to reach us: 112
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