Motorola CPCI-6115 Manuel de service télécharger pdf (Page 171)

Memory Maps and Addresses

CPCI-6200 Installation and Use (6806800J66C)

171

7.4.27.3 Compare Registers

 Tick Timer 1 Compare Register–0xF202_0014 (32 bits)

 Tick Timer 2 Compare Register –0xF202_0024 (32 bits)

 Tick Timer 3 Compare Register–0xF202_0034 (32 bits)

 Tick Timer 4 Compare Register–0xF202_0044 (32 bits)

EN_INT Enable Interrupt

1Interrupt is enabled.

0Interrupt is disabled.

OVF Overflow bits. These bits are the output of the overflow counter. The

overflow counter is incremented each time the tick timer sends an

interrupt to the local bus interrupter. The overflow counter can be

cleared by writing a 1 to the COVF bit.

COVF Clear overflow bits. The overflow counter is cleared when a 1 is written

to this bit.

COC Clear counter on compare

1 Counter is reset to 0 when it compares with the compare

0 Counter is not reset when it compares with the compare

ENC Enable counter

1 Enable the counter increments.

0 Disable the counter increments.

Table 7-55 Tick Timer Control Field Definition (continued)

Table 7-56 Tick Timer Compare Registers

Bit Field Operation Reset

31:0 Tick Timer Compare Value R/W 0

1 2 ... 166 167 168 169 170 171 172 173 174 175 176 ... 195 196

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Motorola CPCI-6115 Manuel de service Page 171