Motorola CPCI-6115 Manuel de service télécharger pdf (Page 77)

Functional Description

CPCI-6200 Installation and Use (6806800J66C)

4.7.2 MRAM (Magnetoresistive Random Access Memory)

This board includes a 512 KB MRAM device that is connected to the processor's local bus. This

memory device provides a non-volatile memory that has unlimited writes, fast access, and long

term data retention without power. The MRAM is organized as 256 K by 16.

4.7.3 Control and Timers PLD

The CPCI-6200 control and timers PLD resides on the local bus. This device provides the

following functions:

 Local bus address latch

 Chip selects for flash banks and real time clock

 System control and status registers

 Four 32-bit tick timers

 Watchdog timer

 Real time clock 1 MHz reference clock

Figure 4-3 Boot Block B

1 2 ... 72 73 74 75 76 77 78 79 80 81 82 ... 195 196

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Motorola CPCI-6115 Manuel de service Page 77