Motorola MVME2400 Series Manuel de service Page 111
- Page / 354
- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
Multi-Processor Interrupt Controller (MPIC) Functional Description
http://www.mcg.mot.com/literature 2-53
2
Interprocessor Interrupts (IPI)
Processor 0 and 1 can generate interrupts which are targeted for the other
processor or both processors. There are four Interprocessor Interrupts (IPI)
channels. The interrupts are initiated by writing a bit in the IPI dispatch
registers. If subsequent IPI’s are initiated before the first is acknowledged,
only one IPI will be generated. The IPI channels deliver interrupts in the
Direct Mode and can be directed to more than one processor.
8259 Compatibility
The MPIC provides a mechanism to support PC-AT compatible chip sets
using the 8259 interrupt controller architecture. After power on reset, the
MPIC defaults to 8259 pass-through mode. In this mode, if the OPIC is
enabled interrupts from external source number 0 (the interrupt signal from
the 8259 is connected to this external interrupt source on the MPIC) are
passed directly to processor 0. If the pass-through mode is disabled and the
OPIC is enabled, the 8259 interrupts are delivered using the priority and
distribution mechanisms of the MPIC.
MPIC does not interact with the vector fetch from the 8259 interrupt
controller.
PHB Detected Errors
PHB detected errors are grouped together and sent to the interrupt logic as
a singular interrupt source. The interrupt delivery mode for this interrupt is
distributed. When the OPIC is disabled the PHB interrupt will be directly
passed on to processor 0 INT pin.
For system implementations where the MPIC controller is not used, the
PHB Detected Error condition will be made available by a signal which is
external to the Hawk ASIC. Presumably this signal would be connected to
an externally sourced interrupt input of a MPIC controller in a different
device. Since the MPIC specification defines external I/O interrupts to
operate in the distributed mode, the delivery mode of this error interrupt
should be consistent.
- MVME2400-Series 1
- VME Processor Module 1
- Programmer’s 1
- Reference Guide 1
- Restricted Rights Legend 2
- ©Copyright Motorola 1999 4
- All Rights Reserved 4
- March 1999 4
- Safety Summary 5
- Safety Depends On You 5
- Contents 7
- Glossary 14
- List of Figures 15
- List of Tables 17
- 1Board Description and 21
- Memory Maps 21
- Overview 23
- Feature Summary 23
- System Block Diagram 24
- 2067 9708 26
- Configuration 36
- PCI MEMORYPROCESSOR 42
- PCI Memory 44
- Processor 44
- ISA Space 44
- PCI I/O Space 44
- ISA Local Resource Bus 49
- VME Registers 51
- Introduction 59
- ❏ Interrupt Controller 60
- Block Diagram 61
- PPC Bus Interface 63
- ❏ HAWK (Highest Priority) 74
- ❏ CPUy (Lowest Priority) 74
- PCI Bus Interface 76
- ❏ Memory and I/O 87
- ❏ Configuration 87
- ❏ Special Cycle 87
- ❏ Interrupt Acknowledge 87
- PPC Address + Offset 88
- PCI Address 88
- 0 0 0 0 0 0 0 88
- Endian Conversion 95
- 1916 9610 96
- Error Handling 98
- Watchdog Timers 99
- PCI/PPC Contention Handling 102
- Functional Description 103
- Transaction Ordering 104
- PHB Hardware Configuration 106
- External Interrupt Interface 108
- Architecture 108
- CSR’s Readability 109
- Interrupt Source Priority 109
- Nesting of Interrupt Events 110
- Spurious Vector Generation 110
- 8259 Compatibility 111
- PHB Detected Errors 111
- Interrupt Delivery Modes 112
- Block Diagram Description 113
- Programming Notes 118
- Operation 120
- Architectural Notes 121
- Registers 123
- MBT Time Out Length 128
- 00 256 µsec 128
- 01 64 µsec 128
- 10 8 µsec 128
- 11 disabled 128
- PCI Registers 153
- $CFB $CFA $CF9 $CF8 162
- $CF8 $CF9 $CFA $CFB 162
- MPIC Registers 166
- Timer 0 - $01100 176
- Timer 0 - $01120 178
- Processor 0 $20080 184
- 3System Memory Controller 187
- Block Diagrams 188
- PowerPC 60x Bus 189
- SDRAMPowerPC 190
- Side Side 190
- PowerPC 60x Bus Interface 199
- ROM/Flash Interface 204
- I2C Interface 209
- Refresh/Scrub 221
- CSR Accesses 221
- External Register Set 221
- Chip Configuration 221
- Programming Model 222
- Table 3-9. Register Summary 223
- ERR_SYNDROME 236
- SBE_COUNT 236
- ERROR_ADDRESS 238
- I2_DATARD 252
- Software Considerations 262
- Possible Control Bit Values 266
- ECC Codes 274
- 4Universe II (VMEbus to PCI) 277
- Registers (UCSR) 283
- Universe II Register Map 284
- Register Name 285
- LSI0_TO 285
- LSI1_TO 286
- LSI2_TO 286
- LSI3_TO 286
- VSI0_TO 288
- VSI1_TO 288
- VSI2_TO 288
- VSI3_TO 288
- VCSR_TO 289
- 5Programming Details 291
- Interrupt Handling 292
- Hawk MPIC 293
- 8259 Interrupts 294
- ISA DMA Channels 297
- Exceptions 298
- Soft Reset 299
- Endian Issues 301
- Figure 5-3. Big-Endian Mode 302
- PCI Local Bus 302
- 60X System Bus 302
- Processor/Memory Domain 304
- MPIC’s Involvement 304
- PCI Domain 304
- Universe II’s Involvement 305
- VMEbus Domain 305
- ROM/Flash Initialization 306
- Ordering Related 307
- Documentation 307
- Manufacturers’ Documents 308
- Publication 309
- Document Title and Source 309
- Related Specifications 311
- MVME2400 VPD Reference 315
- Information 315
- Field Size 319
- VPD data packet 320
- Example VPD SROM 322
- Numerics 341
- 2-87, 2-89 348
- Programmer’s Reference Guide 353
Produits connexes et manuels pour Processeurs Motorola MVME2400 Series
Processeurs Motorola CPU32 Manuel d'utilisateur
(646 pages)
(646 pages)
Processeurs Motorola DSP56800 Spécifications
(28 pages)
(28 pages)
© 2020, manymanuals.fr. Tous droits réservés | 0.730 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels